[cLaRe]

Hi,

Say I have two architectures, A and B with A having complexity of 36 ANDs, 99 XORs. Meanwhile B having complexity of 37 ANDs, 105 XORs. The complexity here is derived directly from its arithmetic properties.

When I compiled both architectures in Quartus, is there any possibility that the architecture A actually requires more LE and Registers compared to architecture B???

thanks

[FvM]

Is it a real problem? Do you mean AND and XOR with only two inputs each? Depending on the actual logic expression, they are combined by Quartus to a smaller amount of either four- or six-input LUTs (depending on the FPGA family). So the required number of LEs can be different. You didn't talk about registers at all.

[BadOmen]

On a Cyclone device for example (4 input LUT) you could have something like this consume a single logic element:

assign x = a & b;
assign y = c & d;
assign z = x & y;

The reason why is in the end z is just a & b & c & d which fits into a 4 input lookup table. FPGAs treat the inputs a-d as the address of the lookup table in the logic element. When you program the FPGA the table has all 16 addresses programmed with the various combinations of a-d. So in the example above addresses 0-14 would be '0' and address 15 would store a '1'. Then when a-d are all high they hit address 15 and a '1' comes out of a LUT.

Like FvM said the results can vary depending on the lookup table size and the logic function you attempt to implement (and what synthesis decides works best). The Stratix II and beyond line of FPGAs include ALUTs which can be split into two lookup tables of various sizes with two registers as well. The logic footprint of FPGAs doesn't directly map to what you would expect from an ASIC since the logic functions are implemented in memory and not gates.

Page 3 of this document gives you a pretty good idea what an logic element looks like: http://www.altera.com/literature/lit-cyc2.jsp

[cLaRe]

Originally Posted by FvM

Is it a real problem? Do you mean AND and XOR with only two inputs each? Depending on the actual logic expression, they are combined by Quartus to a smaller amount of either four- or six-input LUTs (depending on the FPGA family). So the required number of LEs can be different. You didn't talk about registers at all.

The input is just a one byte std_logic_vector and the architecture performs several simple arithmetic using only AND gates and XOR gates.

[cLaRe]

Originally Posted by BadOmen

On a Cyclone device for example (4 input LUT) you could have something like this consume a single logic element:

assign x = a & b;
assign y = c & d;
assign z = x & y;

The reason why is in the end z is just a & b & c & d which fits into a 4 input lookup table. FPGAs treat the inputs a-d as the address of the lookup table in the logic element. When you program the FPGA the table has all 16 addresses programmed with the various combinations of a-d. So in the example above addresses 0-14 would be '0' and address 15 would store a '1'. Then when a-d are all high they hit address 15 and a '1' comes out of a LUT.

Like FvM said the results can vary depending on the lookup table size and the logic function you attempt to implement (and what synthesis decides works best). The Stratix II and beyond line of FPGAs include ALUTs which can be split into two lookup tables of various sizes with two registers as well. The logic footprint of FPGAs doesn't directly map to what you would expect from an ASIC since the logic functions are implemented in memory and not gates.

Page 3 of this document gives you a pretty good idea what an logic element looks like: http://www.altera.com/literature/lit-cyc2.jsp

Thanks! so the logic footprint of FPGA doesnt directly map to what we will obtain from ASIC, how to I justify the real size / throughput achievable from my design?

another question, in FPGA, both AND and XOR utilize the same hardware area and critical path. what in ASIC implementation?

[BadOmen]

I'm not sure of a good way to compare the two design types. You could probably estimate the gate count for an ASIC which would be similar to how I count the LE usage for small blocks of hardware in an FPGA.

In an ASIC I would expect the XOR gate to be larger and slower due to the additional transistors required when compared to an AND gate. Oddly enough I have never implemented an ASIC so I might be oversimplifying things. Just like with FPGAs the sythesis tools may change the footprint to optimize for speed, area, and power.

[cLaRe]

Originally Posted by BadOmen

I'm not sure of a good way to compare the two design types. You could probably estimate the gate count for an ASIC which would be similar to how I count the LE usage for small blocks of hardware in an FPGA.

In an ASIC I would expect the XOR gate to be larger and slower due to the additional transistors required when compared to an AND gate. Oddly enough I have never implemented an ASIC so I might be oversimplifying things. Just like with FPGAs the sythesis tools may change the footprint to optimize for speed, area, and power.

Thanks very much! Now I understand much better =)