[ethstud]

Dear all, after reading the AN570 document on the implementation of the 40G/100G ETH protocol in Stratix IV devices, I have some doubts related on the number of internal Virtual Lanes (VLs). In the document Altera asserts that for the 100G solution, the internal data flow should be given to 20 VLs, while for the 40G solution only to 4 VLs.

The question is simply, why (when for 40G are only 4 VLs) and for 100G 10VLs are not enough? Is here not possible to connect only 10 VLs to 10 FIFOS and 10 Gearboxes, omitting the MUX/Demux?

In the white paper WP-01080-1.2 "Using 10-Gbps Transceivers in 40G/100G Applications", they explain this number as the least common multiple of the electrical (n=10) and PMD(m=?) lanes. But does not a single PMD lane correspond to one 10G transceiver? So in total only 10 10G Transceiver are required to implement a 100G link, leading therefore to a least common multiple of 10, i.e. 10 VLs.

Thank you for the support