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Thread: VHDL Coding Problem Help !!

  1. #1
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    Question VHDL Coding Problem Help !!

    Hello Every One ,
    I have yet another problem with my code. I am having trouble in putting a shift register into my code actually my code provide valid answer after every four clock cycle and i just want to see correct value for which i need to add a shift register but i dont know how to add that in my code . can any one please tell me how i can write it down in my code thanks .the code is shown below.


    Architecture bhv of Polynomial_eveluator is
    Signal reg: integer:=0;
    Begin

    Process
    Begin
    Wait until (clk'event and clk='1');
    If res='1' then reg<=0;
    Else reg<=x*(ai+reg);
    End if ;
    End process;

    fx<=reg+ai;
    End bhv;

  2. #2
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    Default Re: VHDL Coding Problem Help !!

    signal sr : std_logic_vector(31 downto 0);

    begin
    process(clk)
    if (clk'event and clk = '1') then
    sr(0) <= reg(0);
    sr(31 downto 1) <= sr(30 downto 0);
    end if;

    Then just use sr(31) wherever you want.
    If you're new to VHDL, I would recommend not using the type integer unless you know exactly what it's going to get synthesized too. I also usually make the reset asynchronous(common practice, although there are 30 page documents that debate how to do system clears, so anything I say can be debated...)

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    Thumbs up Re: VHDL Coding Problem Help !!

    Thanks RYSC
    i am a newbie to VHDL thats why i am having trouble but thanks for you help i am going to implement this function into my code and hopefully sort out my problem. I will let you know about that Once again thanks .

  4. #4
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    Default Re: VHDL Coding Problem Help !!

    You emailed me but your profile doesn't let you accept email back. I really don't know what problem you're having or what you want to do. The code I pasted should do a shift register(there may be an error like a missing semi-colon or something, I didn't synthesize it). The sr(31) is the last bit shifted out. How big of a shift register are you building? What error are you getting? If everything looks hooked up correctly, then most likely the problem is type conversions(the bane of VHDL newbies and many oldies like myself). You can't just hook one type up to another. Also, the SR I build is one bit, while you may/probably are doing something wider. You could do a 2D array for this, but search the web for examples.

  5. #5
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    Default Re: VHDL Coding Problem Help !!

    thanks Rync,
    when i compiled my program which i have sent u yesterday. my comiler gives me error
    "Error (10001): Verilog HDL or VHDL error at eval.vhd(45): reg does not resolve to a subprogram, type, or array object"
    this error is in this line written below

    sr(0)<= reg(0);

  6. #6
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    Default Re: VHDL Coding Problem Help !!

    I'm not a fan of reg as a name because it's a keyword in verilog. Shouldn't make a difference for VHDL, just pointing it out. The reason I don't like integer is that it's a number with range -2147483647 to +2147483647. So if you're value has a much smaller range, you could be wasting extra logic storing the extra info. Synthesis may prune it down, but now you're relying on synthesis for this. std_logic_vector, signed and unsigned tend to work better because you reference them with the range you want(like 7 downto 0), and you can bit slice them(like grabbing bit 0 or bits 3 downto 0, etc.). I don't use integers and therefore don't have the experience to help you, although you may look at a conversion function. And don't think of it as a conversion function to put it into your shift register. Instead, start with your signal as a more logic typ like std_logic_vector. Then if you have a function like int2vec, convert the std_logic_vector to type int, and pass it into your function. The synthesis tools should have an easier time with this since you're starting off with a defined type that has an exact number of bits, and moving that into the integer range.
    And google the heck out of VHDL and integer, looking for example code and recommendations.

  7. #7
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    Default Re: VHDL Coding Problem Help !!

    This may be a bit off the main topic, but I advise declaring any binary vectors with the unsigned type from ieee.numeric_std, which also includes the conversion function to_integer(unsigned). Also, std_logic_vector and unsigned are closely related types, allowing you to convert one to the other with an type conversion, e.g.

    signal a : std_logic_vector(7 downto 0);
    signal b : unsigned(7 downto 0);

    b <= unsigned(a);

  8. #8
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    Default Re: VHDL Coding Problem Help !!

    i would like to help . but i can find the error form your code. if you can sent me the whole code,maybe i can help you.

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