My PCB design for Cyclone II ep2c20F484;ep2c35F484

[Epis]

I am begginer ir FPGA and the problem I have is with these development bords is that they are very expensive! cheapest bord I found with cyclone II ep2c20 FPGA is firefly bord with cost 350$ and its too expensive and second problem is that these FBGA chips is olmost inposible solder by hands soldering wires to pins.
Only solution is to make PCB and there is third problem that this PCB trace width is wery small 8mils (0.2mm) and ALTERA recomended trace width for PCB is 5mils (0.12mm) and drill hole 8mils (0.2mm) so not all PCB manufacturers can make these PCB and 4 leyer PCB is almost 2.5 times expensiver than 2 leyer PCB.
And I calculated that for me and my frend buying 2bords will cost 700$ and making my own PCB will be mutch cheaper about 300$ for PCB and 100$ for FPGA and ather components.
here is a picture of unfinished PCB

if you don't see the picture go to this link http://theonlyway.net/eoz/upload/attachmen...78&d=1153642561 (it is a forum Where I posted the picture)

There will be availible all IO pins and special purpose pins like those for programming and on bord JTAG conection, 16Mb configuration FLASH, and Power suply circruit for core 1.2V and for IO pins 3.3V
on this bord will be for 3 cyclone devices EP2C20F484;EP2C35F484;EP2C50F484
In 3 PCB leyers I routed out 90 pins on one side so totaly In 3 leyers it is posible to route out 360 pins of FBGA484 package and 4th leyer will be GND and VCC
I am designing this PCB about 2 weaks and previously I designed FBGA 256 package in 2 leyers for EP2C20F256C8 device.
Picture of almost complete 2 leyer PCB designe for EP2C20F256C8 device.

if dont see image go to
http://theonlyway.net/eoz/upload/attachmen...76&d=1153473055

Wen I will finish my designe I will post the picture.
So what you think about my PCB designe is there somthing I missed ?

I plan to develop CNC motion controller to syncronise 4 stepper motors and 1 AC motor with Quadrature encoders, and I olready developed code for motor sinhronization for ATMEL microcontroller Mega128 but it don't work in device and there is too small periperals like PWM generators, 16bit timers, and Input Capture units for all operations thats why I plan to lern FPGA becose ther is no limits you can make so mutch periperals as you need .

[luisalba]

Hi Epis:

It's very important to add series resistor to all JTAG signals and also a 10nf(may be a little bit higher) capacitor near the FPGA pin. The value of the serier resistor maybe will have to be adjust althogh a 47ohm for TDO and 0ohn for the rest can be a good starting point.

Bye,
Luis

[MSchmitt]

i did a migration board with ep2c20f484 and ep2c50f848 both i8n types.

what i miss in your pcb is a proper powersupply layout. those traces conneting vio and vcore are inductance with pure impedance controled traces. imagine what will happen if several hundred or more dff inside your fpga switch from 0 to 1 or vice versa each of them with serveral mA up to hundert mA currents for a few nsec that will lead to a current peak of serveal A/nsec and if you take into account that your voltage ripple has to stay within a few mV you will need caps with low esr.
C(F)=I(A) x t(nsec) / U (V) where U is the max allowed voltage ripple for a time t with a current I. F is As/V
if you now look at these smal traces for the vcore and vio pins and even the gnd pins .... i doubt that you will run a stable design without taking care about gnd bounce over and undershots .... they can lead to uncontrolled switching of your logic as they move the voltage levels for a short time.
My pcb for these FPGAs has 14 Layer and does not need any emc screening to pass emc and etsi approval when running under full load @ 64MHz clock. all signals are impedance controlled. the layout is the key factor for this stable design.

If you have a look at the pcb design guides from altera and xilinx and other you will see that they do not take into account what is realy needed for a stable AND emc bullet proof design. Some of the hints and tips are realy false.

Regards

Michael Schmitt

[Epis]

Thank you for suggestions !
I thought that grounding would be a problem but in thouse ALTERA Power supply articles like http://www.altera.com/support/devices/powe...-integrity.html
there is text of that article ''Designers should add as many 0.2 µF power-supply decoupling capacitors as possible to the VCCINT, VCCIO, and ground pins/planes. Ideally, these small capacitors should be located as close as possible to the device. Designers can decouple each VCCINT or VCCIO and ground pin pair with a 0.2-µF capacitor. If a design uses high-density packages such as ball grid array (BGA) packages, it may be difficult to use one decoupling capacitor per VCCINT / VCCIO and ground pin pair. In such cases, designers make every effort to use as many decoupling capacitors as allowed by the layout. Decoupling capacitors should have a good frequency response, such as monolithic-ceramic capacitors.''

In this FBGA 256 PCB designe http://theonlyway.net/eoz/upload/attachmen...76&d=1153473055
I have place for 9 ceramic capacitors on the Bottom layer for VCC INTernal and For VCC IO I have place for 8 ceramic capacitors on the top layer isn't that enough for EP2C20F256 device if these capacitors are 0.1-0.2uF.
Until now I planed to place in my big FBGA484 PCB desine these small 0.1-0.2uF capacitors as meny as posible in 4th bottom leyer (under FPGA), or I need to make 6 layer PCB 5th layer could be VCC and 6th layer GND.

I planed to use LM2679 ADJ 1.2V 5A Step-down Voltage regulator for internal power supply and for I/O LM2673 3.3V 3A Step-down Voltage regulator as in National Altera designe guide pdf for cyclone FPGA.

[MSchmitt]

It is not only the value of the caps.

maybe i can illustrate the current peaks and what this means with the following ...

imagine you through a stone into the middle of a sea.
The stone is the current peak and the sea is your power supply system.
the current peak is due to switching inside the fpga and other parts.

if it summer, the sea is liquid. The stone will hit the surface and big waves will go out from the impact point. you will see min and max ... same with you power supply the voltage will over and undershot and raise some kind of ringing.
your power supply is too weak

if it is winter, the sea is frozen. the same stone wil hit the same place of the surface with the same energie. the stone will jump up and down ... now think of your power supply system ... not good either

the best is if this sea is like a moor. the same stone will hit the surface and vanish away without resulting waves or a jumping stone. the best solution.

of course you need the big caps. imagine a water supply system for a city. these water tanks will feed the waterpipes (your tracks) but if somebody opens a valve the preasure drops inside that pipe (the voltage on your track)

your smal tracks have to carry the whole current that needs to be delivered to hold the voltage on each fpga pin. i guess you cant do that with traces, you need to do that with power planes. one for each voltage and gnd. these form a capacitor (made by the pcb). the smal caps with a few nF to uF are for haveing low impedance over a wider frequency range.

the fpga 484 footprint needs 5 routing layers to gain access to the inner pins.
how much routing layers are needed for the f256 cant say that out of my head.

I have used the LM2677S-3.3 and a LT3412A for 1.2V a perfect combination here.

a layerstack for the f484 could be

top
gnd
1v2
gnd
3v3
gnd
s1
s2
gnd
s3
s4
gnd
s5
bot

but with 6 layers i cant see a working solution that is stable and will pass all aproval tests.

Michael

[Epis]

I found wery clever solution to reduce your suggested 14 layer designe to 7-8 leyer design by making wery smart design.
Before I will tell my new teory of PCB making look at Sendero Evaluation kit bay microtroniX price 895$ in this Evaluation kit PCB layout they hade only one GND Layer and 2 VCC layers ather were signal layers and totaly they have 8 layer PCB.
So Question is how can they make sutch designe? or they PCB is total garbage!

I read in microtronix home page that they have cutting-edge hardware and software solutions then these sendero bord isn't total garbage and they use big EP2C35F672 device and how then about theyr firefly bords do they olso have 8 layer PCB.

And here is my new PCB routing theory to reduce number of GND planes we can implement these GND fields in signal layer free spaces so 8 layer designe would lock like this:
Top (signal layer 1 and GND)
Signal 2 (gnd)
Signal3 (GND)
Signal 4 (GND)
Signal 5 (GND
Signal 6 (GND)
VCC core (and few signals if there are left some not conected pins)
VCC I/O (and few signals if there are left some not conected pins)

ToTALY we have 6 GND Layers witch is combined with signal layers but to do that we neede to make 4 lines in eatch signal layer to central GND pin block and this is done bay unrouting 3 pins in each side so totaly we will loose 12 pins per layer but as in the end we increase signal layer count bay 3 these lost pins we will route in theas layers.
And I think that it is posible to make even 7 layer bord 5 GND and 2 VCC layers as you suggested, but only combined with Signal layers and finaly it wil be 2 times cheaper than making 14 layer bord!

I think that this is the best solution!

[MSchmitt]

I see the point of reducing the cost for each additional layer pair.
but filling the gaps with gnd polygons is not a power plane.
you will lose the profits you get from a real powerplane design such like low impedance over a wide frequency range. Image a clock of 50Mhz. 50MHz is the first frequency and just a pure sine wave. to reach a rectangle clock shape you need the upper higher frequencies like 150 250 ... so the 5th will give you 250MHz and that means your design must handle at least 250MHz bandwidth.

of course you can get design working with as less a possible layers, but i have seen a couple of pcb's that still work but have no chance to pass emc tests without shielding, ferrit beats and all these expensive stuff. we did the calculation too and we ended up that the 14layers is the cheapest solution over all to get a design that is industrial bullet proof and passes all tests with no metal housing or any shielding. and the peaks are far away from the emc or etsi limits.

filling gaps with gnd can make things more worse as you need to contact them with low impedance to each other, if not you layout some antennas and believe me they will do their job very good and radiate around :-) imagine even a via is a kind of an inductor between your gnd fills with a few pH and a few pF and a bit R so you have R L C what leeds to resonance ...
keeping an eye on the layer stack has on one side the costs for the additional layers but on the other hand you save a lot of caps you do not need to spread around the board. i have a dozend of mlc (each 100uF 6V3 1210size) around the whole pcb and 8 caps 0402 size as a calculated capacitor bank to control the power supply impedance. the copper is there just use it :-) the distance between the layers is also very important. having a distance of 100um between the layers gives you a good power plane but moving to 50um a much better as you gain the goals of field effects between them. but that goes to far here to explain, this is a fpga forum and not an emc.

if i would layout a pcb for my own purpose and will never go to any aproval test i would also try to get rid of any layer pair i can.

take care about the power supply, you will go nut if you try to find out why your design does funny things due to over and undershots. but the fpga's give you the possability to control the current of each pin.

for your layer stack ...
try to have the two power supply layers vcc vio between gnd
signal (gnd)
vcore
signal (gnd)
vcc
signal (gnd)

in this case each power layer has two gnd's one above and the other underneath so you double the cap, halve the impedance .... if your signal does not brake your gnd fills too much

also try to have vcore next to the fpga top layer.

place additional vias to connect the gnds vcc vore tracks fills ... as much as you can to lower the impedance. each signal (track) has a current that travels along this track, but always has a current that goes back ...


Michael Schmitt

[Epis]

Now I will rework my desine (will put larger via holes in central GND block) and then will see if my designe will fit in 6,7 or 8 layers.

6 layer : 8 layer:
signal (gnd) signal (gnd)
gnd only gnd only
vcore (few signal) vcore (few signal)
signal (gnd) signal (gnd)
vcc (few signal) signal (gnd)
signal (gnd) vcc (few signal)
gnd only
signal (gnd)

As I will make les than 50 bords than this leyer count is wery important for me becose price gets significantly higher bay eatch leyer.
here is price comparison of 6,8 leyer bords in PCBCART.com bord size 65mmx75mm, if I make 50 bords then prices are:
6layer;
590$ (1bord 11.8$)
8layer:
862$ (1bord 17.2$)
the diference in price for 1 bord is 5.4 $ and for sutch money I could buy lot of EMI filters for propper grounding.

If I will make fewer bords then this price diference will grow betwen 6 and 8 layer bords. But in high volium production diference will decrease then ofcourse it is cheaper to make 8, 10,.. 14 layer bords without emi filters that reduces total bord cost!

I read some articles about EMI filters and found murata emi noise suppression filters and these chip ferrite beads (which isn't so expensive just 0.03$) could be solution if ground plane can't handle EMI. So I will leave place for these SMD chip emi filters.

[Epis]

Now I decided to make 4layer PCB for ep2c20f256 ep2c8f256 and ep2c5f256 insted of 8layer PCB for ep2c20;35;50 in FBGA484 package becose its to expensive and I dont now how big device I will need, so a good starting point would be ep2c20 in smaler FBGA 256 package.

As I already have routed in 2 layers ep2c20f256 device then i will need to add ground planes and VCC INT,i/o plane.

How much layers these small FPGAs need 4 or 6 ?

If I will need in future larger device then I will make PCB for FBGA672 package becose it covers larger devices than FBGA484.

Wen I will route mu nev 4 layer or 6 layer PCB the I will post link to pictures.

[jdhar]

my god, 14 layers is way too much... you can get a 256BGA on a 6-layer, 4-layer if you don't hav etoo much high speed stuff.

484 can get on a 6-layer very easily. I have put a 672 on an 8-layer, but it could have been dropped to 6 possibly.