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Thread: Verilog design and testbench

  1. #1
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    Default Verilog design and testbench

    How to differentiate verilog design and testbench syntax? Is it depending on the some symbol like #, $ and so on? is all the syntax with symbol for testbench?

    $random is for test bench?

    thanks

  2. #2
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    Default Re: Verilog design and testbench

    Quote Originally Posted by jasonkee111 View Post
    How to differentiate verilog design and testbench syntax? Is it depending on the some symbol like #, $ and so on? is all the syntax with symbol for testbench?

    $random is for test bench?

    thanks
    What is the purpose of this? Do you want to perfom a language detection automatically by your software?

    Verilog:
    `timescale 1 ns / 1 ns
    module simple_counter_top(
    osc_clk,
    rst,
    led
    );

    input osc_clk;
    ...
    endmodule

    VHDL:

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;

    ENTITY simple_counter IS
    PORT
    (
    rst : IN STD_LOGIC;
    osc_clk : IN STD_LOGIC;
    led : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
    );
    END simple_counter;
    ARCHITECTURE bdf_type OF simple_counter IS
    COMPONENT smp_counter
    .....
    end architecture;

  3. #3
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    Default Re: Verilog design and testbench

    Basically, i just want to know the code written(syntax) is for RTL design or testbench. It is because i download the summary of verilog where it contains syntax for testbench and RTL design.

  4. #4
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    Default Re: Verilog design and testbench

    Ok, now I understand. Basically Verilog syntax is the same for a DUT and testbench. The main difference that if the DUT should be synthesized is written in RTL style. RTL style contains mostly only synthesizable constructs, and a testbench can contain whatever you want.
    Generaly a testbench can be recognized that it doesn't have ports, i.e:

    module tb ();

    It has initial block which cannot exist in the DUT. It has a clock generator which cannot be in the RTL style:

    always #5 clk = ! clk;

    And can contain nonsynthesisable tasks as $monitor, $display, $finish etc.

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