I am using a Cyc III/Nios II with the DDR SDRAM HP controller in half rate mode. The controller in half rate mode (to support my SDRAM CAS latency of 2 or 2.5) creates three clocks - the sysclk, auxfull, and auxhalf. Ultimately my CPU is clocked at 100MHz, and the DDR controller is 75MHz (auxhalf) and the DDR memory frequency (auxfull) is 150MHz. So I have a clock crossing bridge in between the cpu and the ddr sdram hp controller. My settings and interconnection is very similar to the Cyclone III EP3C25 dev kit design. Even with the dev kit design from Altera - with maximum effort, the design fails lots of recovery/removal paths related to the clock crossing bridge dcfifo.
No matter how much effort I put into synthesis and the fit - I get many recovery timing errors related to the clock crossing bridge's "DCFIFO". Specifically, the 'FROM' for the failing path always contains the word 'reset' indicating that it's a reset recovery. FYI - the design works and functions 100% properly on the target.
An example failing path is:
Mysystem_SOPC_reset_com_cpu_clk_domain_synch_modul e:Mysystem_SOPC_reset_com_cpu_clk_domain_synch|dat a_out
Mysystem_SOPC_reset_com_cpu_clk_domain_synch_modul e:Mysystem_SOPC_reset_com_cpu_clk_domain_synch|dat a_out -> Mysystem_SOPC:Mysystem_SOPC_inst0|com_cpu_ddr_cloc k_crossing_bridge:the_com_cpu_ddr_clock_crossing_b ridge|com_cpu_ddr_clock_crossing_bridge_downstream _fifo:the_downstream_fifo|dcfifo:downstream_fifo|d cfifo_5tf1:auto_generated|altsyncram_ri31:fifo_ram |q_b