Single FPGA cyclone chip EP1C4F324C8N is configured by using passive serial configuraton with a PowerPC CPU, when system power up from a cold condition, power off for a period of time, such as longer than 5 mins, the FPGA configuration process would fail at beginning, nSTATUS go low during configuration, PowerPC detect this error condition and would keep trying, basically after PowerPC kept trying load FPGA again and again for about 30seconds to 1min, FPGA would be got configured successfully finally, and after that, if recycle power to the system (power up from a warm condition), the FPGA would be loaded successfully in the first time.

I have tried to slow down the clock speed on DCLK, right now it's 200KHz, and I checked signals with scope, they are very clean. I also tried both compressed bitstream file and uncompressed verson, it's the same results. Please give me some advise.