i test g00.. . clock_500 give data be g00 but how can i have input with LDATA & RDATA ??
clock_500 get one data 24bit
clock_500 is datasheet i2sound
PLEASE help me
I had a short look at this audio codec interface, posted at the first page.
It seems, BBcount indirectly controls the 48kpulse and produces someting like:
f = 48kHz = "CLK" / 10 / 50 -> "CLK" = 500 * 48kHz = 24 MHz
Therefore one could change this easily, adapting the counters. The only thing is the DAC information, which also hangs at this clock thing (?)
I would recommend to rewrite it at least to something like this:
(with " CLK / 10 / 50 equals CLK / 4 / 125")
f* = 48kHz * 125 / 10 = 125/10 * "CLK" / 4 / 125
and transform it to an "enable clock" running at 24MHz, obtaining 24 * 5 * 5 = 600MHz for the ALTPLL. Then you get
IN 50 MHz * 12 = 600 MHz
OUT 600 MHz / 25 / 125 = 24 MHz / 125 = 192 kHz
Last edited by fpgaengineerfrankfurt; April 5th, 2012 at 04:58 AM.
Hi, I'm doing speech recognition system by using FPGA, anyone have source code about this project?
You should better have asked that in a new thread.
... and provided some information what you need in detail.
For those you intend to do AUDIO with a 50MHz OSC: There is a relation of MUL/DIV configuration of 57/14 for the PLL which can generate nearly exactly the 64 x Fs frequency = 12.288 which is the S/PDIF frequency. Some OSC tuning will help to synch to an external S/PDIF clock, such as generated by the AUDIO Codecs. I already made this real in some projects.
Last edited by fpgaengineerfrankfurt; August 6th, 2014 at 02:56 PM.
is there any verilog code?