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Thread: DE2 Audio Codec Programming

  1. #21
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    Default Re: DE2 Audio Codec Programming

    Quote Originally Posted by jjclark View Post
    Hello, I am attaching a VHDL file which describes an interface to the Wolfson WM8731 Audio Codec chip located on the Altera DE1 and DE2 boards. This version just does output, but you can augment it to do input. For this you will have to read over the WM8731 datasheet.

    I have tested this on both the DE1 and DE2 boards.

    I hope you find it useful, but there is no warranty implied!

    Jim
    Maybe you could explain to newbie why the code is designed for a 24MHz clock. Doesn't both DE1 and DE2 have 50MHz and 27MHz clocks?

  2. #22
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    Default Re: DE2 Audio Codec Programming

    hi
    i test g00.. . clock_500 give data be g00 but how can i have input with LDATA & RDATA ??
    clock_500 get one data 24bit
    clock_500 is datasheet i2sound
    PLEASE help me

  3. #23
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    Exclamation Re: DE2 Audio Codec Programming

    I had a short look at this audio codec interface, posted at the first page.

    It seems, BBcount indirectly controls the 48kpulse and produces someting like:

    f = 48kHz = "CLK" / 10 / 50 -> "CLK" = 500 * 48kHz = 24 MHz

    Therefore one could change this easily, adapting the counters. The only thing is the DAC information, which also hangs at this clock thing (?)

    I would recommend to rewrite it at least to something like this:
    (with " CLK / 10 / 50 equals CLK / 4 / 125")

    f* = 48kHz * 125 / 10 = 125/10 * "CLK" / 4 / 125

    and transform it to an "enable clock" running at 24MHz, obtaining 24 * 5 * 5 = 600MHz for the ALTPLL. Then you get

    IN 50 MHz * 12 = 600 MHz
    OUT 600 MHz / 25 / 125 = 24 MHz / 125 = 192 kHz
    Last edited by fpgaengineerfrankfurt; April 5th, 2012 at 03:58 AM.

  4. #24
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    Default Re: DE2 Audio Codec Programming

    Hi, I'm doing speech recognition system by using FPGA, anyone have source code about this project?

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