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  Altera Forums > Device and Tools Related > FPGA, Hardcopy, and CPLD Discussion

Real Implementation

 
 
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Old February 8th, 2010, 10:34 AM
cLaRe cLaRe is offline
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Default Real Implementation

Hi,

Say I have two architectures, A and B with A having complexity of 36 ANDs, 99 XORs. Meanwhile B having complexity of 37 ANDs, 105 XORs. The complexity here is derived directly from its arithmetic properties.

When I compiled both architectures in Quartus, is there any possibility that the architecture A actually requires more LE and Registers compared to architecture B???

thanks
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