[faisal_maalik]

Hi

I am designing a video system to buffer three HD 1080p video stream. The input is in RGB 4:4:4 format at 148.5MHz. Output is also the same. I am using Quartus 9.0 SP1.

The system for single HD stream consists of CVI, Frame Buffer and CVO block. Three such blocks are cascaded serially. (There is a custom video processing block but it is outside the SOPC system and not yet connected to the design).

For the SOPC system, I am using 160 MHz clock. For CVI, I am using recovered clock, provided by HDMI chip. For CVO block, output clock is 148.5 MHz, which is generated by local PLL. I am also using DDR2 controller (Microtronix) running at 300 MHz in Startix-III FPGA.

I get the video output but I am also getting Underflows in the video output block and occasional overflow in the video input block. Due to these error, I get a flicker in the output. I have increased the buffer sizes in both these blocks to at lease 4K pixels. I am also using 160MHz clock for SOPC to offset the overhead of Avalon packet generation. But still cannot get rid of these Overflow and underflows. I dont know what else can I do to solve this problem. I'll be very thankful if someone can give any insight or suggestions.


Regards
Faisal