Threads
: 19,055
Posts
: 77,931
Members
: 29,419
Welcome to our newest member,
The_General
User
Reputation
FvM
9142
jakobjones
7620
Rysc
5941
Daixiwen
4200
thepancake
3030
kaz
2197
MSchmitt
2056
pletz
1706
Tricky
1388
kevin
1300
*Reputation Information
User Name
Remember Me?
Password
Register
Quick Search
Advanced Search
Altera Forums
>
General
>
General Altera Discussion
Search Forums
Show Threads
Show Posts
Advanced Search
Go to Page...
Multicycle question
Thread Tools
Display Modes
Prev
Next
#
1
February 8th, 2010, 09:02 PM
ereeves
Altera Pupil
Join Date: Dec 2008
Posts: 6
Rep Power:
627
Multicycle question
If I setup an adder with a clk enable and an output latency of 2 clks, is it necessary to specify a multicycle constraint between the clk enable and the adder output?
Thanks.
ereeves
View Public Profile
Send a private message to ereeves
Find all posts by ereeves
«
Previous Thread
|
Next Thread
»
Thread Tools
Show Printable Version
Email this Page
Display Modes
Switch to Linear Mode
Switch to Hybrid Mode
Threaded Mode
Posting Rules
You
may not
post new threads
You
may not
post replies
You
may not
post attachments
You
may not
edit your posts
vB code
is
On
Smilies
are
On
[IMG]
code is
On
HTML code is
Off
Forum Jump
User Control Panel
Private Messages
Subscriptions
Who's Online
Search Forums
Forums Home
General
General Altera Discussion
Altera Forum Website Related
Jobs at Altera
Device and Tools Related
FPGA, Hardcopy, and CPLD Discussion
Quartus II and EDA Tools Discussion
IP and Dev Kit Related
IP Discussion
DSP Builder and DSP IPs
Nios Forum
General Discussion
General Discussion Forum
General Software Forum
Nios II C-to-Hardware Acceleration
Nios Wiki
Operating Systems
Linux Forum
Innovateasia Contest - Linux for Nios II
ecos Forum
MicroC/OS-II Forum
Nucleus Forum
Development Kit Related
University Program
Shared Material
Shared Material
Similar Threads
Thread
Thread Starter
Forum
Replies
Last Post
multicycle path
kevin007
General Altera Discussion
5
May 19th, 2009
09:04 AM
Applying multicycle assignments
kwalt
Shared Material
2
August 29th, 2008
02:30 PM
clock enable multicycle
roberts
Quartus II and EDA Tools Discussion
3
January 23rd, 2008
11:00 AM
Multicycle period & Multicycle hold
David_Cai
Quartus II and EDA Tools Discussion
3
January 22nd, 2008
06:41 AM
Multicycle Custom Instructions
saiprashanth
General Discussion Forum
0
May 22nd, 2006
03:43 AM
All times are GMT -8. The time now is
12:00 PM
.
»
FPGA, CPLD and ASIC: Altera
  »
Bay Area Web Design
Contact Admin for Website Issues
-
Altera Forums
-
Archive
-
Top