[Shev]

I wrote my component using Verilog and now try to integrate it to the Nios II embedded Evaluation Kit System. It's a part of Ethernet module (recive-part), and contains to input ports for MII interface (RX_DV and RXD - conduit typei n SOpc builder) and 3 ports for a conection with Avalon Bus.
I used a Example from nios II evaluation kit v8.0, created a new component in Sopc-builder (.tcl file attached in a .zip, besides there is a top-flie of the component) and added new component to the SOpc system. Then I generated a sopc system and compiled my quartus project. After compilation I did't find in the Pin Planner RX_DV and RXD ports of my component, and of course in the top-file of my project.
Other problem: my component should work, using Clk from MII (from the peripheral phy-level device, not from Avalon bus). But Sopc-bulder doesn't permit me to make Clk and
Could you help to solve this problems?