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Thread: crc 32 bit & 32 bit data

  1. #1
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    Post crc 32 bit & 32 bit data

    Hi all
    here i wrote vhdl code for 32 bit crc for 2 bits of input data. please can anybody ulter this code
    for 32 bits of input data.If u have any other vhdl or verilog code (CRC-32 and 32 bit data) please forward to me.Here i attached a document,which was used for writing below vhdl code.waiting for positive reply...


    Vhdl code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity CRC_BLOCK is
    port (
    fcsut std_logic_vector(31 downto 0);
    CLK:in std_logic;
    data:in std_logic_vector(1 downto 0);
    Reset_n:in std_logic);
    end CRC_BLOCK;
    architecture Behavioral of CRC_BLOCK is
    begin
    process(CLK)
    variable Dividend: std_logic_vector(34 downto 0);--make it 34 and check
    variable quo1:std_logic_vector(31 downto 0);
    variable rem1: std_logic_vector(33 downto 0);
    variable g:integer;
    variable polynomial:std_logic_vector(32 downto 0);--G(X)
    constant n:std_logic_vector(32 downto 0):="100000000000000000000000000000000";
    begin
    if(CLK'event and CLK = '1')then
    if(Reset_n = '0')then
    quo1 := (others=>'0');
    polynomial:="100000100110000010001110110110111";
    dividend := data * n;--M(X)*X32
    rem1(33 downto 0):=dividend(33 downto 0);
    fcs(31 downto 0) <= rem1(31 downto 0);
    else
    if (g=1) then
    quo1:= (others=>'0');
    else

    if(rem1 >= polynomial )then
    rem1 (0) := rem1(1) xor polynomial(0);
    rem1 (1) := rem1(2) xor polynomial(1);
    rem1 (2) := rem1(3) xor polynomial(2);
    rem1 (3) := rem1(4) xor polynomial(3);
    rem1 (4) := rem1(5) xor polynomial(4);
    rem1 (5) := rem1(6) xor polynomial(5);
    rem1 (6) := rem1(7) xor polynomial(6);
    rem1 (7) := rem1(8) xor polynomial(7);
    rem1 (8) := rem1(9) xor polynomial(8);
    rem1 (9) := rem1(10) xor polynomial(9);
    rem1 (10) := rem1(11) xor polynomial(10);
    rem1 (11) := rem1(12) xor polynomial(11);
    rem1 (12) := rem1(13) xor polynomial(12);
    rem1 (13) := rem1(14) xor polynomial(13);
    rem1 (14) := rem1(15) xor polynomial(14);
    rem1 (15) := rem1(16) xor polynomial(15);
    rem1 (16) := rem1(17) xor polynomial(16);
    rem1 (17) := rem1(18) xor polynomial(17);
    rem1 (18) := rem1(19) xor polynomial(18);
    rem1 (19) := rem1(20) xor polynomial(19);
    rem1 (20) := rem1(21) xor polynomial(20);
    rem1 (21) := rem1(22) xor polynomial(21);
    rem1 (22) := rem1(23) xor polynomial(22);
    rem1 (23) := rem1(24) xor polynomial(23);
    rem1 (24) := rem1(25) xor polynomial(24);
    rem1 (25) := rem1(26) xor polynomial(25);
    rem1 (26) := rem1(27) xor polynomial(26);
    rem1 (27) := rem1(28) xor polynomial(27);
    rem1 (28) := rem1(29) xor polynomial(28);
    rem1 (29) := rem1(30) xor polynomial(29);
    rem1 (30) := rem1(31) xor polynomial(30);
    rem1 (31) := rem1(32) xor polynomial(31);
    rem1 (32) := rem1(33) xor polynomial(32);
    quo1 := quo1 + 1;

    end if;
    if(rem1 >= polynomial )then
    rem1(32 downto 0) := rem1(31 downto 0) & '0';
    rem1 (0) := rem1(0) xor polynomial(0);
    rem1 (1) := rem1(1) xor polynomial(1);
    rem1 (2) := rem1(2) xor polynomial(2);
    rem1 (3) := rem1(3) xor polynomial(3);
    rem1 (4) := rem1(4) xor polynomial(4);
    rem1 (5) := rem1(5) xor polynomial(5);
    rem1 (6) := rem1(6) xor polynomial(6);
    rem1 (7) := rem1(7) xor polynomial(7);
    rem1 (8) := rem1(8) xor polynomial(8);
    rem1 (9) := rem1(9) xor polynomial(9);
    rem1 (10) := rem1(10) xor polynomial(10);
    rem1 (11) := rem1(11) xor polynomial(11);
    rem1 (12) := rem1(12) xor polynomial(12);
    rem1 (13) := rem1(13) xor polynomial(13);
    rem1 (14) := rem1(14) xor polynomial(14);
    rem1 (15) := rem1(15) xor polynomial(15);
    rem1 (16) := rem1(16) xor polynomial(16);
    rem1 (17) := rem1(17) xor polynomial(17);
    rem1 (18) := rem1(18) xor polynomial(18);
    rem1 (19) := rem1(19) xor polynomial(19);
    rem1 (20) := rem1(20) xor polynomial(20);
    rem1 (21) := rem1(21) xor polynomial(21);
    rem1 (22) := rem1(22) xor polynomial(22);
    rem1 (23) := rem1(23) xor polynomial(23);
    rem1 (24) := rem1(24) xor polynomial(24);
    rem1 (25) := rem1(25) xor polynomial(25);
    rem1 (26) := rem1(26) xor polynomial(26);
    rem1 (27) := rem1(27) xor polynomial(27);
    rem1 (28) := rem1(28) xor polynomial(28);
    rem1 (29) := rem1(29) xor polynomial(29);
    rem1 (30) := rem1(30) xor polynomial(30);
    rem1 (31) := rem1(31) xor polynomial(31);
    rem1 (32) := rem1(32) xor polynomial(32);
    end if;
    if (rem1 > polynomial) then
    fcs(31 downto 0) <= rem1(31 downto 0);
    g:=1;
    end if;
    end if;
    end if;
    end if;
    end process;
    end Behavioral;
    Attached Files Attached Files

  2. #2
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    Default Re: crc 32 bit & 32 bit data

    Your keyboard may look somewhat worn out? How about using XOR for an aggregate or vector?
    Code:
    rem1 (32 downto 0) := rem1(33 downto 1) xor polynomial(32 downto 0);

  3. #3
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    Default Re: crc 32 bit & 32 bit data

    Basically, CRC can be calulated either parallel or sequential, one bit per clock cycle. I have difficulties to see the algorithm behind your code, but this may due to insufficient reading. I wouldn't expect a multiply operator, however.

    Personally, I prefer to use the Quartus crc compiler or code from the internet as:
    http://www.think-silicon.com/ipgeniu...=CRC_generator
    http://www.opencores.org/projects.cg...e_crc/overview

  4. #4
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    Default Re: crc 32 bit & 32 bit data

    Hi FvM
    I'm getting crc values continuiously with each clock cycle. Can u tell me which CRC value is used in frame check sequence (FCS)?
    Whether i need to make "enable" signal high for only one clock cycle ? So i can get single CRC value. I did't find any polynominals
    G (X) used in this code.
    Can u tell me how to calculate "NewCRC" values, because in data sheet i didn't find any algorithm for calculating "NewCRC" values.
    Waiting for your reply...

    In first clock cycle=rst=0 then rst=1
    in second cycle init=1 then init=0
    In third cycle enable is made high.
    serialin=data in_msb

    Verilog code:
    module CRC32_8( clk,
    rstn,
    enable,
    init,
    D, //DataIn
    CRC, //CRC
    match //set if CRC=0
    );
    input clk;
    input rstn;
    input enable;
    input init;
    input [7:0] D;
    output [31:0] CRC;
    output match;

    wire [31:0] C;
    wire [31:0] NewCRC;
    reg [31:0] CRC;
    reg match;

    always @ (posedge clk )
    begin
    if(rstn==0) begin
    CRC [31:0] <= {32{1'b1}};
    match <= 1'b0;
    end
    else
    begin
    if(init) begin
    CRC [31:0] <= {32{1'b1}};
    match <= 1'b0;
    end
    else
    if(enable)
    begin
    CRC <= NewCRC;
    if (CRC==32'd0)
    match<=1'b1;
    else
    match<=1'b0;
    end
    end
    end

    assign C = CRC;
    assign NewCRC[0] = D[6] ^ D[0] ^ C[30] ^ C[24];
    assign NewCRC[1] = D[7] ^ D[6] ^ D[1] ^ D[0] ^ C[31] ^ C[30] ^ C[25] ^ C[24];
    assign NewCRC[2] = D[7] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ C[31] ^ C[30] ^ C[26] ^ C[25] ^ C[24];
    assign NewCRC[3] = D[7] ^ D[3] ^ D[2] ^ D[1] ^ C[31] ^ C[27] ^ C[26] ^ C[25];
    assign NewCRC[4] = D[6] ^ D[4] ^ D[3] ^ D[2] ^ D[0] ^ C[30] ^ C[28] ^ C[27] ^ C[26] ^ C[24];
    assign NewCRC[5] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[31] ^ C[30] ^ C[29] ^ C[28] ^ C[27] ^ C[25] ^ C[24];
    assign NewCRC[6] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[31] ^ C[30] ^ C[29] ^ C[28] ^ C[26] ^ C[25];
    assign NewCRC[7] = D[7] ^ D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[31] ^ C[29] ^ C[27] ^ C[26] ^ C[24];
    assign NewCRC[8] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[28] ^ C[27] ^ C[25] ^ C[24] ^ C[0];
    assign NewCRC[9] = D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[29] ^ C[28] ^ C[26] ^ C[25] ^ C[1];
    assign NewCRC[10] = D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[2] ^ C[29] ^ C[27] ^ C[26] ^ C[24];
    assign NewCRC[11] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[3] ^ C[28] ^ C[27] ^ C[25] ^ C[24];
    assign NewCRC[12] = D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ D[0] ^ C[4] ^ C[30] ^ C[29] ^ C[28] ^ C[26] ^ C[25] ^ C[24];
    assign NewCRC[13] = D[7] ^ D[6] ^ D[5] ^ D[3] ^ D[2] ^ D[1] ^ C[5] ^ C[31] ^ C[30] ^ C[29] ^ C[27] ^ C[26] ^ C[25];
    assign NewCRC[14] = D[7] ^ D[6] ^ D[4] ^ D[3] ^ D[2] ^ C[6] ^ C[31] ^ C[30] ^ C[28] ^ C[27] ^ C[26];
    assign NewCRC[15] = D[7] ^ D[5] ^ D[4] ^ D[3] ^ C[7] ^ C[31] ^ C[29] ^ C[28] ^ C[27];
    assign NewCRC[16] = D[5] ^ D[4] ^ D[0] ^ C[8] ^ C[29] ^ C[28] ^ C[24];
    assign NewCRC[17] = D[6] ^ D[5] ^ D[1] ^ C[9] ^ C[30] ^ C[29] ^ C[25];
    assign NewCRC[18] = D[7] ^ D[6] ^ D[2] ^ C[31] ^ C[30] ^ C[26] ^ C[10];
    assign NewCRC[19] = D[7] ^ D[3] ^ C[31] ^ C[27] ^ C[11];
    assign NewCRC[20] = D[4] ^ C[28] ^ C[12];
    assign NewCRC[21] = D[5] ^ C[29] ^ C[13];
    assign NewCRC[22] = D[0] ^ C[24] ^ C[14];
    assign NewCRC[23] = D[6] ^ D[1] ^ D[0] ^ C[30] ^ C[25] ^ C[24] ^ C[15];
    assign NewCRC[24] = D[7] ^ D[2] ^ D[1] ^ C[31] ^ C[26] ^ C[25] ^ C[16];
    assign NewCRC[25] = D[3] ^ D[2] ^ C[27] ^ C[26] ^ C[17];
    assign NewCRC[26] = D[6] ^ D[4] ^ D[3] ^ D[0] ^ C[30] ^ C[28] ^ C[27] ^ C[24] ^ C[18];
    assign NewCRC[27] = D[7] ^ D[5] ^ D[4] ^ D[1] ^ C[31] ^ C[29] ^ C[28] ^ C[25] ^ C[19];
    assign NewCRC[28] = D[6] ^ D[5] ^ D[2] ^ C[30] ^ C[29] ^ C[26] ^ C[20];
    assign NewCRC[29] = D[7] ^ D[6] ^ D[3] ^ C[31] ^ C[30] ^ C[27] ^ C[21];
    assign NewCRC[30] = D[7] ^ D[4] ^ C[31] ^ C[28] ^ C[22];
    assign NewCRC[31] = D[5] ^ C[29] ^ C[23];
    endmodule

  5. #5
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    Default Re: crc 32 bit & 32 bit data

    If you are referring to PPP 32-bit FCS option, it uses CCITT-32 polynomial, the FCS calculation is documented in RFC1570.It's the polynomial 0x04C11DB7 respectively 0xEDB88320 used in your previous code. In a parallel CRC algoritm as shown above, the polynomial has been compiled to the respective bit terms. I didn't check, if it's the right one, but you should be able by pencil-and-paper method.

    The shown code is very straightforward to my opinion, except for identifying the used polynomial. Enable must me set for one clock, when a new data byte is present at the input. Care must be always taken with correct bit order, so I suggest to check against a known good example or the original specification.

    The code can be easily tested in Quartus simulator, I think.
    Last edited by FvM; May 24th, 2008 at 03:18 AM.

  6. #6
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    Default Re: crc 32 bit & 32 bit data

    I've developed an online tool that can generate parallel CRC with arbitrary data and polynomial sizes. It's on http://OutputLogic.com.

    Hope it helps

    - Evgeni

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