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Thread: help for audio codec using VHDL

  1. #11
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    Default Re: help for audio codec using VHDL

    Quote Originally Posted by FvM View Post
    The code should be published at the Altera Wiki. It's much more instructive than the respective Terasic demonstration projects.
    Thanks for the tip. I am creating a website which will have reference designs from our school and was going to post a link to it on these forums. But, I will publish this code and others at Altera wiki as well (once I have cleaned them up a bit).

    Have a great week.

    Bart

  2. #12
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    Default Re: help for audio codec using VHDL

    thank you again i have now been able to configure the mic in line in and out ............. sorry to bother you again but i want another help how do i use the data of mic in.......... in your program i can use ta line in data but how to use the mic in data???

  3. #13
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    Default Re: help for audio codec using VHDL

    well i have been able to find the sloution thank you ......... now i am going for CDMA ............

  4. #14
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    Default Re: help for audio codec using VHDL

    Hello,

    I have tried to replicate the project from mbharat.
    But I always get errors like:
    Error: Port "acknowledge" does not exist in macrofunction "i2cController"
    (same with done, i2c_scl, i2c_sda, readWriteEnable and start)

    Do I have the wrong I2C_Controller.v?

    Edit: I also have the DE1 board.

  5. #15
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    Default Re: help for audio codec using VHDL

    Quote Originally Posted by moou View Post
    Hello,

    I have tried to replicate the project from mbharat.
    But I always get errors like:
    Error: Port "acknowledge" does not exist in macrofunction "i2cController"
    (same with done, i2c_scl, i2c_sda, readWriteEnable and start)

    Do I have the wrong I2C_Controller.v?

    Edit: I also have the DE1 board.
    I didn't post a .v file, my hardware is described using VHDL. Thanks.

    Bart

  6. #16
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    Default Re: help for audio codec using VHDL

    thanks for the fast reply,

    I know that you dont posted a v. file, but I only have the i2c controller from the demonstrations of altera.

    I do not know where I can get an appropriate VHDL.
    To rewirte the existing .v to .vhd I understand not much enough verilog.

  7. #17
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    Default Re: help for audio codec using VHDL

    Quote Originally Posted by moou View Post
    thanks for the fast reply,

    I know that you dont posted a v. file, but I only have the i2c controller from the demonstrations of altera.

    I do not know where I can get an appropriate VHDL.
    To rewirte the existing .v to .vhd I understand not much enough verilog.
    Oh, I think I understand: your tried to port Terasic's audio codec verilog source to VHDL?

    To answer your question about appropriate VHDL, I had earlier posted in this thread my .VHDL audio codec interface. You can first just try to synthesize that and see if it works. Then you should go about reading the audio codec datasheet and try to understand the VHDL I posted. Mind you my i2c controller is not the best, I am working on an updated version. I will post that as soon as I am done.

    Second, as far as Terasic's audio codec verilog is concerned, I just resynthesized their HDL (from /DE1_CD_v0.8/DE1_i2sound/) on version 10.0 of Quartus. It synthesized fine, I didn't get any errors.

    Bart

  8. #18
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    Default Re: help for audio codec using VHDL

    as someone pointed out, the code is very clear and I think really useful.
    I've managed to use it with an i2c controller ported from altera's one, and the waveform generation just works fine. if i try loopback i have this result (with signal on line in):
    sw0+sw9 up: hex0 stuck on "5", static. every time i switch sw0 down and then up, static (volume varying between trials).

    basically, board now adds static to signal input, if present, or just plays static if no signal input is present. any hints? am I missing something?

    thank you in advance,
    best regards

    C

  9. #19
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    Default Re: help for audio codec using VHDL

    It's the same with me too.
    But again in brief.
    sw0 on & (sw8 sw9) off -> sine wave
    sw0 on & sw9 off & sw8 on -> square wave
    it is up to here is the same as in the comments:)

    sw0 on & sw9 on & sw8 off -> adc-dac-loopback + noise


    But mbharat will publish his code when he has once again revised.
    Stay tuned :) .
    Last edited by moou; January 7th, 2011 at 02:03 AM.

  10. #20
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    Default Re: help for audio codec using VHDL

    Hey,

    @carlo.bono: I believe my master FSM is designed to go through the initialization routine only once and get to a "stop" state. Hence you see a "5" (or "S" ) on HEX0 where I output the current state of the master FSM. However the static is a more serious issue. But you say that you have a new i2c routine? However if your waveform generation works fine, why do you say the board adds static if no signal input is present? I am wondering if my interface to the data registers has issues with the new i2c routine.

    @ moou: Thanks for the vote of confidence, it will be another couple of weeks before I can get all the information up. I am designing a website that will incorporate all the course materials we have for digital systems at the Milwaukee School of Engineering (where I am an assistant prof.). This should include stuff on basic concepts, VGA, audio, NIOS, student projects etc. but all targeted for the DE1.

    I will post a link on the Altera wiki once this is done but it is taking me a while because of all the material I have to organize. But it should be done in a couple of weeks.

    Bart

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