Hi all, i'm a newbie in vhdl coding and i'm trying to execute a vhdl code written by another person in quartus 2.
He has written it using Aldec Active HDL 8.2.This code in Active HDL compiles but not in Quartus 2.
Below I post the relevant code
When i compile the code, i have an error on the row highlighted (there's also the ' but it doesn't appear in php window) and it's this one:
entity project is
port( IR:in std_logic_vector(7 downto 0);
architecture arch of project is
control_logic_req: process (IR, other parameters)
if (IR event) then --error here
Error (10302): VHDL attribute error at project.vhd(158): attribute "event" that is used for multiple bits is not synthesizable
Now i wonder
1) why it compiles in Active HDL and not in Quartus 2 with the same file .vhd? Does it need some additive library?
2) in quartus 2 how can i fix this problem?
Thanks everybody for your advices.