Results 1 to 5 of 5

Thread: [VHDL] Problem with 'event attribute on std_logic_vector signal

  1. #1
    Join Date
    Mar 2011
    Posts
    2
    Rep Power
    1

    Default [VHDL] Problem with 'event attribute on std_logic_vector signal

    Hi all, i'm a newbie in vhdl coding and i'm trying to execute a vhdl code written by another person in quartus 2.
    He has written it using Aldec Active HDL 8.2.This code in Active HDL compiles but not in Quartus 2.
    Below I post the relevant code

    PHP Code:
    entity project is
             port
    (  IR:in std_logic_vector(7 downto 0);     
    ...
    end project;

    architecture arch of project is
    ...

    control_logic_reqprocess (IRother parameters)
    if (
    IR 'event) then --error here
    ... 
    When i compile the code, i have an error on the row highlighted (there's also the ' but it doesn't appear in php window) and it's this one:
    Error (10302): VHDL attribute error at project.vhd(158): attribute "event" that is used for multiple bits is not synthesizable

    Now i wonder
    1) why it compiles in Active HDL and not in Quartus 2 with the same file .vhd? Does it need some additive library?
    2) in quartus 2 how can i fix this problem?

    Thanks everybody for your advices.
    Last edited by tinezridan; March 2nd, 2011 at 12:43 AM.

  2. #2
    Join Date
    Oct 2008
    Location
    UK
    Posts
    2,801
    Rep Power
    1

    Default Re: [VHDL] Problem with 'event attribute on std_logic_vector signal

    Quartus is synthesis tool and only supports the synthesis subset of vhdl.
    In this subset an edge event is translated to clocked flipflop. You can only have one clock per flip. So the clock signal must be one bit.

    If Aldec compiles it then you ned to know what is the outcome of compilation, it could be just simulation toolset.

    Anyway I advise you to write your own code. The worst thing is wasting time to port mystery codes across tools.

  3. #3
    Join Date
    Oct 2008
    Posts
    3,704
    Rep Power
    1

    Default Re: [VHDL] Problem with 'event attribute on std_logic_vector signal

    the problem is that

    if IR'event then

    is perfectly legal VHDL, which is why it compiles in ActiveHDL (this ia just a simulator and development environment). It will work perfectly fine in a simulator. an event occurs any time IR changes. When it comes to Quartus, it has to map this behaviour on to real hardware, which it cannot do, as extra circuitry is required that detects changes in IR, that is not described in the VHDL. You would usually compare a registered version of IR to the current value of IR.

    Im guessing the origional designer intended it to be used in this way, but does not understand how hardware works.

    Edit - just to add, are you sure this isnt a VHDL model? its quite common to use VHDL like this in models rather than synthesisable code.

  4. #4
    Join Date
    Mar 2011
    Posts
    2
    Rep Power
    1

    Default Re: [VHDL] Problem with 'event attribute on std_logic_vector signal

    Thank kaz and Tricky for your answers...
    Yes, it's a model and was not designed to be implemented on a specific hardware. I wanted to use Quartus 2 because this software is familiar to me (I used it with verilog).

    Is there a synthesizable way to code this part without using event attribute?

  5. #5
    Join Date
    Oct 2008
    Posts
    3,704
    Rep Power
    1

    Default Re: [VHDL] Problem with 'event attribute on std_logic_vector signal

    It really depends on what the code is doing. yes you probably can make it synthesisable, but if its a model using code like this elsewhere, it probably needs a complete re-write.

Similar Threads

  1. VHDL std_logic_vector Comparisons
    By sluong771 in forum General Altera Discussion
    Replies: 8
    Last Post: December 20th, 2010, 11:20 PM
  2. [VHDL] Problem with signal type "std_logic_vector(0 downto 0)"
    By Szymo in forum FPGA, Hardcopy, and CPLD Discussion
    Replies: 4
    Last Post: May 21st, 2010, 05:13 AM
  3. Confusion on signal attribute HIGH
    By m26k9 in forum General Altera Discussion
    Replies: 4
    Last Post: March 9th, 2010, 09:11 AM
  4. Audio signal signed or std_logic_vector
    By mesbah2u in forum University Program
    Replies: 1
    Last Post: February 24th, 2009, 02:22 PM

Bookmarks

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •