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Thread: How to supress hierarchy optimizer for logic cells?

  1. #11
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    Default Re: How to supress hierarchy optimizer for logic cells?

    Hi Jerry!
    The FPGA part number used was EP2C70F896C6.
    Actually, by the documentation each lcell brings about 447ps delay.
    I got the 4.25ns by simulation and oscilloscope
    I had change a lot of things meanwhile and finished it about July/2011. My last code for the pulse delay module is this:

    Code:
    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    
    ENTITY pd IS
    	PORT
    	(
    		pulse 	:in std_logic;
    		pulse_d	:out std_logic
    	);
    end pd;
    
    architecture beha of pd is
    	
    -- N gives the pulse delay multiplier. pulse_delay = N*lcell_delay
    -- N must be adjusted to be coherent to pulse_delay desired and lcell_delay of using device
    -- logic cell delay can be found in device performance documentation
    	constant N : integer := 17;
    -- lcell array with N elements
    	signal delay_line: std_logic_vector(N-1 downto 0);
    -- these attributes force synthesizer to keep our buffer alone :)
    -- this ensures that delay is the expected
    	attribute keep: boolean;
    	attribute keep of delay_line: signal is true;
    	
    	begin
    	gen_delay:
    	for i IN 1  TO N-1 generate
    	delay_line(i) <= delay_line(i-1);
    	end generate;
    	delay_line(0) <= pulse;
    	pulse_d <= delay_line(N-1);
    end beha;
    This is easier to change, as if you need more or less delay per instance you just need to increase or decrease, respectively, the constant N value.
    The delay value will be N*lcell_delay.

    Hope this can be helpful

    Cheers,
    Mateus

  2. #12
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    Default Re: How to supress hierarchy optimizer for logic cells?

    Quote Originally Posted by mazzeo View Post
    Hi Jerry!
    The FPGA part number used was EP2C70F896C6.
    Actually, by the documentation each lcell brings about 447ps delay.
    I got the 4.25ns by simulation and oscilloscope
    I had change a lot of things meanwhile and finished it about July/2011. My last code for the pulse delay module is this:

    Code:
    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    
    ENTITY pd IS
        PORT
        (
            pulse     :in std_logic;
            pulse_d    :out std_logic
        );
    end pd;
    
    architecture beha of pd is
        
    -- N gives the pulse delay multiplier. pulse_delay = N*lcell_delay
    -- N must be adjusted to be coherent to pulse_delay desired and lcell_delay of using device
    -- logic cell delay can be found in device performance documentation
        constant N : integer := 17;
    -- lcell array with N elements
        signal delay_line: std_logic_vector(N-1 downto 0);
    -- these attributes force synthesizer to keep our buffer alone :)
    -- this ensures that delay is the expected
        attribute keep: boolean;
        attribute keep of delay_line: signal is true;
        
        begin
        gen_delay:
        for i IN 1  TO N-1 generate
        delay_line(i) <= delay_line(i-1);
        end generate;
        delay_line(0) <= pulse;
        pulse_d <= delay_line(N-1);
    end beha;
    This is easier to change, as if you need more or less delay per instance you just need to increase or decrease, respectively, the constant N value.
    The delay value will be N*lcell_delay.

    Hope this can be helpful

    Cheers,
    Mateus
    Dear mazzeo:

    thanks for you reply, it's very useful for me.

    for the lcell's delay value, where do you find from datasheet? i mean, can you point me which paper, which chapter?

  3. #13
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    Default Re: How to supress hierarchy optimizer for logic cells?

    Hi
    Actually, it's not easy to find... :P
    You can see here: ftp://ftp.altera.com/up/pub/datashee..._cii5v1_01.pdf

    Go to page 99, Table 516 (LE_FF Internal Timing Microparameters) and see the last row:

    tLUT 447ps for 6 speed grade (the one on DE2-70).

    This parameter gives you the time between the input and output of a LUT. This is the lcell delay.

    Hope this is helpful

    Cheers,
    Mateus

  4. #14
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    Default Re: How to supress hierarchy optimizer for logic cells?

    Quote Originally Posted by mazzeo View Post
    Hi
    Actually, it's not easy to find... :P
    You can see here: ftp://ftp.altera.com/up/pub/datashee..._cii5v1_01.pdf

    Go to page 99, Table 516 (LE_FF Internal Timing Microparameters) and see the last row:

    tLUT 447ps for 6 speed grade (the one on DE2-70).

    This parameter gives you the time between the input and output of a LUT. This is the lcell delay.

    Hope this is helpful

    Cheers,
    Mateus
    Thank you very much!!!
    it's very useful for me!

    but, it also doesn't provide the carry chain delay time,
    Last edited by Jerry; March 29th, 2012 at 05:55 PM.

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