Would someone please explain "tightly coupled memory" and its use within the NiosII/Qsys context?
The exercise manual section of the "Designing with the Nios II Processor and Qsys" Customer Training handout (A-MNL-NII-QSYS-1DAY-11-0-v1) states that s1 of the On-Chip Memory (dual-port) should be connected to the Nios II tightly_coupled_instruction_master_0 interface and s2 of the On-Chip Memory should be connected to the Nios II data_master interface.
HOWEVER, the Qsys connection diagram on the same page shows s2 of the On-Chip Memory connected to the Nios II instruction_master interface.
So... which one is correct, and why do I need the tightly-coupled instruction master anyway?
Should I also include a tightly-coupled data master if I use a data cache?
BTW - I discovered previously that I need a data cache in the Nios II to properly interface with my 16-bit wide SRAM chip.