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Thread: Using ALTPLL and ALTCLKCTRL (Clock Muxing)

  1. #1
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    Default Using ALTPLL and ALTCLKCTRL (Clock Muxing)

    I have 3 clocks that I want to select which clock to use for a certain part of my subsystem. 2 clocks are generated from the internal PLL and one is a external clock source.

    Although the concept and code seems simple I keep on getting this error.:

    Error: inclk[1] port of Clock Control Block "altclkctrl0:inst2|altclkctrl0_altclkctrl_6df:altc lkctrl0_altclkctrl_6df_component|clkctrl1" is driven by pll_device:inst|altpll:altpll_component|_clk1, but must be driven by a clock pin

    I tried to change around the ordering of my 3 clocks to the different pins of the ALTCLKCTRL and I still get a variation of the above warning.

    Anyone have any insight why I am having this problem?


    Code:
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    
    entity clock_device is
    port (
         clk : in std_logic;
         en : in std_logic;
         clk_sel : in std_logic_vector(1 downto 0);
        out_clk : out std_logic
             );
    end clock_device;
    
    architecture behavior of clock_device is
    
    component clock_pll 
        port
        (
            inclk0        : IN STD_LOGIC  := '0';
            c1        : OUT STD_LOGIC ;
            c2        : OUT STD_LOGIC
        );
    end component;
    
    component clock_switch
        PORT
        (
            clkselect        : IN STD_LOGIC_VECTOR (1 DOWNTO 0) :=  (OTHERS => '0');
            ena        : IN STD_LOGIC  := '1';
            inclk0x        : IN STD_LOGIC ;
            inclk1x        : IN STD_LOGIC ;
            inclk2x        : IN STD_LOGIC ;
            outclk        : OUT STD_LOGIC 
        );
    end component;
    
    signal temp_c0,temp_c1 : std_logic;
    
    
    begin
    
    
    
    clockpll : clock_pll port map(
        inclk0 => clk,
        c1    => temp_c0,
        c2    => temp_c1
    );
    
    clockswitch : clock_switch port map(
            clkselect => clk_sel,
            ena     => en,
            inclk0x    => clk,
            inclk1x    => temp_c0,
            inclk2x    => temp_c1,
            outclk    => out_clk
     ); 
     
    end;

  2. #2
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    Default Re: Using ALTPLL and ALTCLKCTRL (Clock Muxing)

    If you turn to the help on ALTCLKCTRL in Quartus II, you'll see there are some restrictions in connecting the input ports to different clock sources.

    inclk[0] and inclk[1] need to be driven by clock pins and inclk[2] and inclk[3] need to be driven by a PLL clock output.

    So in your case, you need to instantiate a ALTCLKCTRL with four input ports: inclk0x, inclk1x, inclk2x and inclk3x. Connect inclk2x to temp_c0,
    inclk3x to temp_c1, inclk0x to clk. Connect inclk1x to '0'.

    Then you will pass the compilation

  3. #3
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    Default Re: Using ALTPLL and ALTCLKCTRL (Clock Muxing)

    Actually, be sure to look in the device handbook. For pretty much all devices, the altclkctrl can only switch dynamically between outputs of a single PLL. There is no way to mux in the original clk. (The reason the altclkctrl has all its possible connections documented is because it is the global clock tree driver, so it's documenting how things get onto it, but most connections are static based on the bitstream.) If the two outputs of the PLL do not match the input clock's frequency, create another PLL output tap that does and use that.

  4. #4
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    Default Re: Using ALTPLL and ALTCLKCTRL (Clock Muxing)

    @wdshen: This is true, however you do not have to connect the clocks up this way as the fitter will rearrange them for you. Changing the order of his clock connections will not fix his problem.

    @Rysc: You can actually mux in the input clock with the PLL outputs. I didn't think you could either, but I tried it and it works.

    @Supaflyfrank: The error you are getting seems to indicate that your input clock is not on a dedicated clock pin, which is a requirement for the ALTCLKCTRL. Did you assign pins in your design? The fitter will automatically put the input clock on a clock pin, which is why I'm asking.

    I've attached at test design using Quartus II 11.1 in a Stratix IV device that shows that your code should work. Sorry, but I used Verilog. I'm not a VHDL guy.
    Attached Files Attached Files

  5. #5
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    Default Re: Using ALTPLL and ALTCLKCTRL (Clock Muxing)

    Hi jimbo,

    Rysc is right in saying the solution is device dependent.

    The solution I proposed is based on Cyclone III. For Cyclone III, we must generate ALTCLKCTRL megafunction with four clock inputs, if we want to implement the function supaflyfrank needs.

    The way I connect these clocks to ALTCLKCTRL is just an example. The only restriction is that the two PLL clocks must go to inclk3x and inclk4x. The input clock pin can go to either inclk0x or inclk1x, with the remaining unused input connected to '0'. The interesting thing is, I find out, that you can't even connect the remaining unused input to '1' or input clock pin. The compilation would fail. You can only connect it to '0' to pass the compilation.

    I think the help text on ATLCLKCTRL in Quartus II is not precise for every device. Because in your example, it is OK to just use three clock inputs of ATLCLKCTRL in Stratix. But definitely that won't work in Cyclone. Cyclone needs four clock inputs. Also, when we generate ATLCLKCTRL in Megawizard, we get sightly different options based on the target device.

    So, supaflyfrank, the actual solution depends on the device you use.

  6. #6
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    Default Re: Using ALTPLL and ALTCLKCTRL (Clock Muxing)

    Yes, it appears that for Cyclone III (and maybe all Cyclone families?), that this does produce the error unless you create the MegaWizard for 4 inputs of the ALTCLKCTRL. This sounds like a bug to me as I see no reason why the fitter couldn't do the same thing it does for Stratix IV and just rearrange the inputs. If you create all 4 inputs on the ALTCLKCTRL and leave input[0] unconnected, you won't get the error. You end up with the exact same implementation as with Stratix IV. You can still bring the input clock to the PLL into the ALTCLKCTRL. I'll file an SPR for this.

  7. #7
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    Default Re: Using ALTPLL and ALTCLKCTRL (Clock Muxing)

    Altera Software has acknowledged the problem and is investigating it. It is currently set to be fixed in 12.0. In the meantime, you have a workaround by using all 4 inputs and leaving the inclk0 input unconnected.

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