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Thread: verilog-module instantiation

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    Default verilog-module instantiation

    hi all... currently working on a project, i have a top level module (module A), with a module instantiated in it ,module B. I just have one question. When does the system know when to start running module B ?

    in module A, i have all the input to module B declared and assigned. However, at certain point of the codes, where there are supposed to have output from module B, the system just seems not running module B. When i simulated using modelsim, all the variables in module B are 'x'.
    any clue why is this happening ? or did i make any mistakes anywhere ? please advice...thanks...

    p/s: sorry if i make my question complicated...i am still new to verilog...

  2. #2
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    Default Re: verilog-module instantiation

    Everytime I've done that, it's because I forgot to drive something into the module, it became unknown and propogated around. You said you're driving everything, but maybe worth a double-check.
    I think modelsim has a tracex capability, where you can trace an x back to where it came from. I only used it once and struggled to figure it out(I have very little modelsim experience), so maybe someone else can post more details?

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    Default Re: verilog-module instantiation

    ya, confirmed that i drive all the inputs into the module.
    i thought that if we drive all the necessary inputs to the module, it should start operating and come up with an output...no ?

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    Default Re: verilog-module instantiation

    Is the output dependent on something that might not be initialized like a flip flop or RAM in module B?

    Also I would double check signal widths in both modules to make sure signals are not getting truncated somewhere in your logic. I'm not sure if there is a way to check for this in Modelsim but the Quartus II synthesis engine should issue you a warning when this happens.

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    Default Re: verilog-module instantiation

    Quote Originally Posted by BadOmen View Post
    Is the output dependent on something that might not be initialized like a flip flop or RAM in module B?
    sorry, but i don't really understand this question. There is output from module B that i need in module A.
    perhaps i will just provide you guys with parts of the code to make things clear.

    Code:
    module A;
    
      reg [15:0] s, sq, sqe;
      reg [3:0] q;
      reg [4:0] s_length, q_length, sqe_length;
      reg subset_start;
      wire subset_out,subset_done;
      
      
      B mod_B(q,q_length,sqe,sqe_length,subset_start,subset_out,subset_done);
    
    always @*
      begin
        subset_start=0;                             
        cS=3'd 1;
        
        s=s_in[s_in_length-1];
        s_length=5'd 1;
        
        q=s_in[s_in_length-2];
        q_length=5'd 1;
    
        sq={s,q[0]};
        sqe=sq>>1;
        sqe_length=s_length+q_length-1;
        subset_start=1;
    (some codes here)
    
    
    case (subset_out)
          1: begin
    .
    .
    .
    
    (some codes here)
    end
    
         0:begin
    .
    .
    .
    (some codes here)
    end
    
    end
    endmodule
    
    
    module B(q,q_length,sqe,sqe_length,start,out,done);
      
      input start;
      input [4:0] q_length;
      input [3:0] q;
      input [15:0] sqe;
      input [4:0] sqe_length;
      output reg out,done;
    always @ (posedge start)
      begin
    .
    .
    .
    (codes)
    end
    endmodule

    as you can see, i had initialized every input to module B. i'm just wondering why i can't get any output out of it. Module B wasn't executing where it should be.

    the variable "subset_start" in module A was used to trigger the always block in module B. Can i do something like this ? Or i did it in the wrong way ?
    Last edited by cjYee; March 1st, 2012 at 04:40 PM.

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    Default Re: verilog-module instantiation

    I meant initialize registers/RAMs in the submodule. I see in module B you have some sort of net with sensitivity to 'start' but without seeing that net I have no clue what you have implemented. If your intent was to create a flipflop you should be driving it with a clock and reset as well and using an enable bit if you don't want it to capture every clock cycle. If you don't drive a reset into a register at the beginning of the simulation you'll get unknown data out of it (Modelsim can't assume high or low outputs from unitialized regs/RAMs). There are templates in Quartus II under the edit menu you can take a look at for typical hardware blocks such as registers, memory, etc...

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    Default Re: verilog-module instantiation

    As shown above, module A has no in- or ouputs. But there are undefined signals like s_in. I think. it's pointless to discuss the problem details at this level of information.

    There are basically three possible reasons:
    - missing simulation stimulus
    - the output depends on the state of uninitialized internal signals, as discussed by BadOmen
    - missing data path in the internal logic

    As Rysc metioned, Modelsim has perfect means to trace where the unexpected ouput comes from.

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    Default Re: verilog-module instantiation

    actually module A do have inputs and outputs. I just didn't include them here because my main concern is on the module instantiation. I just want to show that the input to module B are defined. So just ignore the inputs and output of module A.
    And, module B is not a register/RAM nor a flipflop...what i m trying to do is, i want to make module B a function, that i could call anytime i want, like in C language. Can it works this way? I did it wrong ?

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    Default Re: verilog-module instantiation

    You mean that module B is pure combinational. That's possible of course.

    I just want to show that the input to module B are defined.
    Defined yes, but we can't see if all variables are initialized as well. Apparently they aren't.

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    Default Re: verilog-module instantiation

    Quote Originally Posted by FvM View Post
    You mean that module B is pure combinational. That's possible of course.
    so did i did it the correct way ? please advice...
    Last edited by cjYee; March 4th, 2012 at 02:17 AM.

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