I would like to simulate a very simple design in SystemVerilog and to compare the results of RTL and gate level simulation. The RTL simulation works OK but if I launch the gate level simulation the ModelSim reports:
# ALTERA version supports only a single HDL
# ** Fatal: (vsim-3039) D:/... failed.
# FATAL ERROR while loading design
# Error loading design
# Error: Error loading design
Can anybody help me? Many thanks in advance.