Thank's for the fast answer. My VHDL experience are not the best. This is a new section for me.
Yes, that's right. I have to convert std_logic_vector in unsigned / signed. Can i use integer too?
So, my idea for the implementation:
Is it the right way? But do i need a clk?
type table is Array (natural range <>) of std_logic_vector (7 downto 0);
constant vec_value: table := ("00000000","00000001","00000010","00000010","00000010","00000110","00010010");
signal tmp : unsigned := "00000000" ;
if clk'event and clk = '1' then
for i in 0 to 6 loop
tmp <= tmp + unsigned(vec_value(i));
SUM <= (tmp,8);
For the first time to lean about arithmetic operations i use constant's but later it will be elements of memory which are frequently change
The question is, will vec_value always be a constant, or is it some kind of memory?
Thank's a lot