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Thread: Error: top level design entity " " is undefined

  1. #1
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    Thumbs up Error: top level design entity " " is undefined

    we have problem in compiling VHDL code in Quartus II software. Every time we compile it shows the Error:top level design entity " file name" is undefined.

    We are even taking care of the case sensitivity.

    Our file name, new created project name and entity name in the code are all same.

    Plz help us regarding this.

  2. #2
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    Default Re: Error: top level design entity " " is undefined

    Quote Originally Posted by saranyakumarasamy View Post
    we have problem in compiling VHDL code in Quartus II software. Every time we compile it shows the Error:top level design entity " file name" is undefined.

    We are even taking care of the case sensitivity.

    Our file name, new created project name and entity name in the code are all same.

    Plz help us regarding this.
    Hi,

    did you set the toplevel correctly ? You can check that in Quartus :

    Assignments -> Device -> General

    Look to the field "Toplevel entity". If this is not your toplevel, write it down here.

    Kind regards

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    Thumbs up Re: Error: top level design entity " " is undefined

    Hi,
    thanks for the reply..
    I tried to check the top level entity in the way u said but it is the same name as in program. It is all in small case.
    Still there is undefined top level entity error.

    Should the file name be in small case also?

    Is it got to do with the location of the file where it is stored?

    Thanks

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    Default Re: Error: top level design entity " " is undefined

    Try to avoid the space character in the name, sometimes it has created strange behaviour.

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    Thumbs up Re: Error: top level design entity " " is undefined

    Hi...

    Thanks for the reply....

    There is no space character in the name.
    Is there any specific location like 'bin' folder where the files has to be stored while simulating the program?

    Please help me with this..
    Thanks

  6. #6
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    Default Re: Error: top level design entity " " is undefined

    Quote Originally Posted by saranyakumarasamy View Post
    Hi...

    Thanks for the reply....

    There is no space character in the name.
    Is there any specific location like 'bin' folder where the files has to be stored while simulating the program?

    Please help me with this..
    Thanks
    Hi,

    you can check whether the file is in the project or not.

    Project -> Add/Remove Files in Project

    There you can see all the files which are used in the project.
    If you don't see your top-level files use the "add" button to include the file.
    Btw: Did you use the Project wizard for setting up your project ?

  7. #7
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    Default Re: Error: top level design entity " " is undefined

    The said error message means, that no entity with the said top-level name can be found in any of the design files, the error can clearly be distinguished from file not found.

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    Default Re: Error: top level design entity " " is undefined

    Quote Originally Posted by FvM View Post
    The said error message means, that no entity with the said top-level name can be found in any of the design files, the error can clearly be distinguished from file not found.
    Hi FvM,

    when the top-level file isn't in the file list, you don't get any message about a missing file.


    Did you get a warning like this during Analysis and Elaboration ?

    Warning: Can't analyze file -- file C:/altera/quartus80sp1/qdesigns/vhdl_verilog_tutorial/addersubtractor.vhd is missing
    Last edited by pletz; November 2nd, 2008 at 05:56 AM.

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    Default Re: Error: top level design entity " " is undefined

    hello, I met with the same question,

  10. #10
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    Default Re: Error: top level design entity " " is undefined

    Quote Originally Posted by aqaqaq View Post
    hello, I met with the same question,
    As FvM indicated this error message is caused by the fact that no VHDL entity is found with the name of the "Top Level Entity". It is not enough to name your VHDL file with the name of the top entity. The top entity itself of your VHDL description should have this name.

    e.g. In the example below TOP is the "Top Level Entity" and has been declare d like that (see @pletz) file TOP.vhd

    entity TOP is
    port (
    ...
    );
    end TOP;


    architecture my_design of TOP is
    begin
    ...
    end my_design;

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