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Thread: Stratix III - Quartus web edition 11.0

  1. #1
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    Default Stratix III - Quartus web edition 11.0

    Hi, everyone

    My university has a XD2000i from xtremedata. XD2000 has a Stratix III EP3SE260F1152C3.

    On Altera's download page, I've found out that Quartus 11.0 web edition lists EP3SE260F1152C3 as a
    supported device. Then I downloaded version 11.0 and installed. The device appears in the list, but when
    I start synthesis, this error appears:

    There is no valid device available

    Am I doing something wrong, or EP3SE260F1152C3 is only available in subscription edition?

  2. #2
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    Default Re: Stratix III - Quartus web edition 11.0

    According to this:

    http://www.altera.com/literature/po/...rtussevswe.pdf

    Web Edition Stratix support = None.

    You will require the subscription edition. You should be able to get the subscription edition for free via the University Program. Have your professor contact them.

    Cheers,
    Dave

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    Default Re: Stratix III - Quartus web edition 11.0

    Can we get two versions? The XD2000's manual is from 2009 and recommends to use quartus v8.1. I was going to try
    v11 to see if it works, since 8.1 is already an old version. But I'm afraid that we get stuck with v8.1 because of manual
    optimizations and settings made by xtremedata.

    Thanks for your reply!

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    Default Re: Stratix III - Quartus web edition 11.0

    Can we get two versions?
    The subscription license is not on a per version basis. I typically have several versions of Quartus installed.

    The XD2000's manual is from 2009 and recommends to use quartus v8.1. I was going to try
    v11 to see if it works, since 8.1 is already an old version. But I'm afraid that we get stuck with v8.1 because of manual
    optimizations and settings made by xtremedata.
    The XD2000 is just an FPGA in co-processor socket. Whatever optimizations they made in Quartus 8.1 will be available, or unnecessary in 12.1sp1.

    I would recommend installing 8.1 to ensure you can build a design that meets timing. The timing constraints will be in Classic Timing Analyzer format. To synthesize in 12.1sp1, you will need to convert the timing constraints to TimeQuest SDC format. I would recommend doing that manually, so that you are forced to understand where the original timing constraints came from, eg., the processor specification for the socket that the FPGA replaces.

    Cheers,
    Dave

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    Default Re: Stratix III - Quartus web edition 11.0

    Again, thanks for your reply!

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