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Thread: problem (?) using shared variables

  1. #21
    Tricky is offline Moderator **Forum Master**
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    Default Re: problem (?) using shared variables

    you shouldnt use clk_en to generate a clock. Forget about generating a 2nd clock. Just use the clk_en directly.

  2. #22
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    Default Re: problem (?) using shared variables

    Quote Originally Posted by Tricky View Post
    you shouldnt use clk_en to generate a clock. Forget about generating a 2nd clock. Just use the clk_en directly.
    Hi,

    Based on your recommendation, I developed the following code:
    Code:
    library ieee;
    use ieee.std_logic_1164.all;
    
    entity clock_gen is
       generic(N: integer := 10);
       port(
          mclk:  in std_logic;
          rst:  in std_logic;
          clk: out std_logic);
    end clock_gen;
    
    architecture arch of clock_gen is
       signal cnt: integer := 0;
    begin
       process(mclk, rst)
       begin
          if(rst = '1') then
             cnt <= 0;
    	 clk <= '0';
          elsif(rising_edge(mclk)) then
             cnt <= cnt + 1;
    	 if(cnt = N) then -- this will give you an enable rate of clk/N
                clk <= '1';
             else
                clk <= '0';
             end if;
          end if;
       end process;
    end arch;
    The simulation of this code produced the following result:

    one_pulse_simulation.jpg

    A "return to zero" was needed. Also, I would prefer a 50% duty cycle clock generator. So I did some modifications on your recommendation and produced the following code:

    Code:
    library ieee;
    use ieee.std_logic_1164.all;
    
    entity clock_gen is
       generic(N: integer := 20);
       port(
    	   mclk:  in std_logic;
               rst:  in std_logic;
    	   clk: out std_logic);
    end clock_gen;
    
    architecture arch of clock_gen is
       signal    cnt: integer := 0;
    begin
       process(mclk, rst)
       begin
          if(rst = '1') then
             cnt <= 0;
    	 clk <= '0';
          elsif(rising_edge(mclk)) then
             cnt <= cnt + 1;
    	 if(cnt >= (N - 1)/2) then -- this will give you an enable rate of clk/N
                if(cnt = (N - 1)) then
                   clk <= '0';
    	       cnt <= 0;
    	    else
    	       clk <= '1';
    	    end if;
             else
                clk <= '0';
             end if;
          end if;
       end process;
    end arch;
    Regards
    Jaraqui

  3. #23
    Tricky is offline Moderator **Forum Master**
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    Default Re: problem (?) using shared variables

    This is the point, you're not supposed to generate a 50% duty cycle, as the "other" bit of code should also be using mclk as the clock. But it is only enabled with clk_en (hence it only works one in every N clocks)

  4. #24
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    Default Re: problem (?) using shared variables

    Quote Originally Posted by Tricky View Post
    This is the point, you're not supposed to generate a 50% duty cycle, as the "other" bit of code should also be using mclk as the clock. But it is only enabled with clk_en (hence it only works one in every N clocks)
    Sorry Tricky, my English is not so good... I didnīt understand very well this last message. Could you explain in other words, please?

  5. #25
    Tricky is offline Moderator **Forum Master**
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    Default Re: problem (?) using shared variables

    The problem is, you're generating a clock. You should never generate a clock. You should clock all logic with mclk. Then use clock_en to activate it:

    Code:
    process(mclk)
    begin
      if rising_edge(mclk) then
        if clk_en = '1' then
          --only do something when clk_en is active, say 1 in every 50
        end if;
      end if;
    end process;
    So this way divides your clock without having any problems associated with a generated clock.

  6. #26
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    Default Re: problem (?) using shared variables

    Quote Originally Posted by Tricky View Post
    The problem is, you're generating a clock. You should never generate a clock. You should clock all logic with mclk. Then use clock_en to activate it:

    Code:
    process(mclk)
    begin
      if rising_edge(mclk) then
        if clk_en = '1' then
          --only do something when clk_en is active, say 1 in every 50
        end if;
      end if;
    end process;
    So this way divides your clock without having any problems associated with a generated clock.
    Ok! Now I understood! Thank you!

    Regards
    Jaraqui

  7. #27
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    Default Re: problem (?) using shared variables

    The main use for shared variables is in test benches

    have a look at OSVVM. ORG

    the free packages there make extensive use of SHARED VARIABLES


    They are also very useful verification packages.

    creating good stimulus is often a lot of work & is boring.

    SAVE YOURSELF A LOT OF WORK

    have a look at intelligent coverage at OSVVM. ORG

    Those packages can create intelligent random functional coverage stimulus for you.

    With very little effort from you they can create stimulus for all the functions you ask them to cover in your testbench.

    They are written by Jim Lewis & he leads the IEEE VHDL standard group who are working on the next version of VHDL after VHDL2008.

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