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Thread: Verilog code for sine pulse width modulation

  1. #1
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    Default Verilog code for sine pulse width modulation

    Hello every one.. I am very new to this quartus II, which I am using with FPGA (cyclone II). I have written some code for sine pulse width modulation (PWM) method, but after flashing that code into FPGA, I didn't got any pulses. I don't know where i am making the mistake. And I don't know how to assign the FPGA pins for checking the output. Please check the code and help me, please please... here i am pasting my code and logic for sine PWM. here i am using counter as a triangle wave at 10khz, for 50Mhz clock. Please find the attachments.
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    Default Re: Verilog code for sine pulse width modulation

    The sine generator is very simple Cordic implementation known to work, but the ramp generator is scrap. Check it's operation with pencil and paper method or in a simulation. You need at least an up_down state variable. As shown, it will only count one step back and forth.

    You also need to scale either sine or ramp signal. Now you are comparing 16 bit ramp (13.2 Bit utilized) with 8 Bit sine range.

    Finally, a signed variable must be declared as such in Verilog, all variables are unsigned by default.
    Last edited by FvM; September 10th, 2013 at 11:15 PM.

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    Default Re: Verilog code for sine pulse width modulation

    Thanks FvM.. You please go through my code once.. There i have used cordic algon for sine generation (i found it on internet), please tell whether it is correct or not.. And in that sine wave code how to change the amplitude and frequency.. And for triangle (or ramp) generation, i have used counter, you please check that code also.. In my logic counter will increase in steps of 1 with clock frequency, after it is reaching to particular peak it will decrease.. That peak will decide the frequency of triangle.. Suppose my clock freq=50Mhz, and i want 10Khz triangle, then the peak is (50M/10K = 5000). I am thinking like this, please tell me if i am wrong. So please check my code which i have attached and tell the modification. This forum is my only hope, my supervisor is not helping.. please...

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    Default Re: Verilog code for sine pulse width modulation

    As I already told, the ramp generator does not work. Please reconsider it's basic operation.

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    Default Re: Verilog code for sine pulse width modulation

    Please tell me if this code is correct..

    module sine_cos(clock, reset, en, sine, cos);
    input clock, reset, en;
    output [7:0] sine,cos;
    reg [7:0] sine_r, cos_r;
    assign sine = sine_r + {cos_r[7], cos_r[7], cos_r[7], cos_r[7:3]};
    assign cos = cos_r - {sine[7], sine[7], sine[7], sine[7:3]};
    always@(posedge clock or negedge reset)
    begin
    if (!reset) begin
    sine_r <= 0;
    cos_r <= 120;
    end else begin
    if (en) begin
    sine_r <= sine;
    cos_r <= cos;
    end
    end
    end
    endmodule

    module triangle(clock, reset, triangle);
    input clock, reset;
    output[7:0] triangle;
    reg[7:0] triangle;
    reg[7:0] counter;
    reg[7:0] updown;
    always@(posedge clock or negedge reset)
    begin
    if(reset) begin
    counter <= -125;
    updown <= 0;
    end
    else if (rising_edge(clock))
    begin
    if (updown == 0)
    if (counter < 125)
    begin
    counter <= counter + 5;
    end

    if (counter == 120)
    begin
    updown <= 1;
    end

    else if (updown == 1)
    if (counter >-125)
    begin
    counter <= counter - 5;
    end

    if (counter == -120)
    begin
    updown <= 0;
    end
    end
    end
    always@(posedge clock or negedge reset)
    begin
    if(reset) begin
    triangle <= counter;
    end
    end
    endmodule


    module PWM(triangle, cos, pwm, clock);
    input triangle, cos, clock;
    output pwm;
    reg pwm;
    reg [15:0] counter = 0;

    always @ (posedge clock)

    begin
    if (cos >= triangle) pwm = 1;
    else pwm = 0;
    end
    endmodule

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