Before we start - I am a QSYS beginner, and a newcommer to embedded IP.
I am trying to connect the Altera TSE MAC to the HPS. All existing examples use a NIOS, FPGA DMA controllers and a large internal RAM for packet buffering. As the HPS should have it's own DMA engine, should I be able to connect the TX and RX ports of the TSE MAC to the AXI ports of the HPS, as I thought they accepted streaming and MM?
Do I still need to do what the other examples do - use a Scatter gather DMA controller? Instead of an onboard ram, can I just connect the memory ports to the SDRAM connected to the HPS (obviously restricting memory space?)