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Thread: Using PLL "lock" signal as the async reset in Verilog

  1. #11
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    Default Re: Using PLL "lock" signal as the async reset in Verilog

    Thanks very much, Dave.
    You're welcome!

    Cheers,
    Dave

  2. #12
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    Cool Re: Using PLL "lock" signal as the async reset in Verilog

    Quote Originally Posted by dwh@ovro.caltech.edu View Post
    You do not want to use PLL lock as a reset signal directly. Not all PLL locked outputs have a debounce/deglitch filter, so they may toggle for a while before they stay in a static state.

    Download the code associated with this PCIe test

    http://www.alteraforum.com/forum/showthread.php?t=35678

    There's a deglitch/debounce filter in there you can use to "clean-up" the locked signal. You can then decide whether to use the "clean" signal as a synchronous or asynchronous reset signal.

    Cheers,
    Dave
    Hi Dave,

    First of all I hope you don't mind about my english, it's not my mother language. I'd like to know why you set the locked filter time to 0.5ms (25000 cycles in 50MHz), since Cyclone IV DS indicates Tlock = 1ms I figured out it might be set to 50000. Can you tell me more about it?

    Thank's!

    Anderson

  3. #13
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    Default Re: Using PLL "lock" signal as the async reset in Verilog

    Quote Originally Posted by dwh@ovro.caltech.edu View Post
    This is synthesizeable - it tells the compiler what the initial register state is in the download bit-stream.
    Would this be the 'initial' block?? Or is there something else?
    Last edited by Numinus1; January 2nd, 2017 at 12:50 AM. Reason: later realisation

  4. #14
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    Default Re: Using PLL "lock" signal as the async reset in Verilog

    Would this be the 'initial' block?? Or is there something else?
    Synthesis tools do not support initial blocks very consistently. If you want to have an FPGA power-up with a particular value in a register you can assign that value during the initialization of the signal. For example;

    logic [31:0] regA = 32'h12345678;
    signal regA : std_logic_vector(31 downto 0) := X"12345678";

    You can chose to override these values in the reset part of a clocked process.

    Cheers,
    Dave

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