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Thread: Using PLL "lock" signal as the async reset in Verilog

  1. #1
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    Default Using PLL "lock" signal as the async reset in Verilog

    If I want to use the PLL "lock' signal to work as an async reset, the "lock" signal will keep low after the FPGA is powered and goes high after a duration. If I won't reset my PLL, then it means "lock" siganl will never have a falling edge. If I power off the FPGA and power it again, it will have another rising edge.

    In this case, can I still write the Verilog as following:

    always @(posedge clk or negedge lock)
    begin

    if (lock == 1'b0)

    else


    end


    As I mentioned previously, since there is no falling edge for "lock", will the Verilog code work? I guess it will but I am not sure.

    Thanks in advance.

  2. #2
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    Default Re: Using PLL "lock" signal as the async reset in Verilog

    You do not want to use PLL lock as a reset signal directly. Not all PLL locked outputs have a debounce/deglitch filter, so they may toggle for a while before they stay in a static state.

    Download the code associated with this PCIe test

    http://www.alteraforum.com/forum/showthread.php?t=35678

    There's a deglitch/debounce filter in there you can use to "clean-up" the locked signal. You can then decide whether to use the "clean" signal as a synchronous or asynchronous reset signal.

    Cheers,
    Dave

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    Default Re: Using PLL "lock" signal as the async reset in Verilog

    Quote Originally Posted by dwh@ovro.caltech.edu View Post
    You do not want to use PLL lock as a reset signal directly. Not all PLL locked outputs have a debounce/deglitch filter, so they may toggle for a while before they stay in a static state.

    Download the code associated with this PCIe test

    http://www.alteraforum.com/forum/showthread.php?t=35678

    There's a deglitch/debounce filter in there you can use to "clean-up" the locked signal. You can then decide whether to use the "clean" signal as a synchronous or asynchronous reset signal.

    Cheers,
    Dave

    Hi Dave,

    Thanks very much to mention this. I will be very careful to use the lock of PLL as the reset.

    I still want to be clear about my question. Let's assume the lock from PLL is a clean signal. Can I write the verilog code as my previous post?

    Thanks very much.

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    Default Re: Using PLL "lock" signal as the async reset in Verilog

    Let's assume the lock from PLL is a clean signal. Can I write the verilog code as my previous post?
    Yes. For example, lets say you have an external reset (from a reset supervisor) and your PLL lock signal. A simple register would be ...

    Code:
    assign rstN = lock & ext_rstN;
    
    always @ (posedge clk or negedge rstN)
    if (~rstN) 
       q <= 1'b0;
    else 
       q <= d;
    However, keep in mind that you would normally want to synchronize the reset source to each clock domain, i.e., rstN should be synchronized to clk, otherwise you will run into reset timing issues.

    Cheers,
    Dave

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    Default Re: Using PLL "lock" signal as the async reset in Verilog

    Quote Originally Posted by dwh@ovro.caltech.edu View Post
    Yes. For example, lets say you have an external reset (from a reset supervisor) and your PLL lock signal. A simple register would be ...

    Code:
    assign rstN = lock & ext_rstN;
    
    always @ (posedge clk or negedge rstN)
    if (~rstN) 
       q <= 1'b0;
    else 
       q <= d;
    However, keep in mind that you would normally want to synchronize the reset source to each clock domain, i.e., rstN should be synchronized to clk, otherwise you will run into reset timing issues.

    Cheers,
    Dave

    Thanks very much, Dave. Yes, I need to synchronize the reset otherswise I may have problem in reset deassert.

    The example you took is a little different from what I mentioned since the " external reset " will have the falling edge. But just assume I don't have this external reset, I only have "lock" signal as the reset and I won't have falling edge in normal case, can I still put :

    negedge lock into the always sensitive list?

    Or ask in anther way, if there is only low voltage level in "lock", there is no falling edge, whether this lock signal can still trigger the reset or not?

    Thanks very much.

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    Default Re: Using PLL "lock" signal as the async reset in Verilog

    if there is only low voltage level in "lock", there is no falling edge, whether this lock signal can still trigger the reset or not?
    If you use lock as an active-low reset, and it never goes high, then your logic will remain in reset.

    Conversely, if you have an active low reset signal, eg., rstN, and it never goes low, the reset condition will never occur. You will see this in simulation, in that a signal will never take on its reset value, but instead will take on the default value for the data type used in the process. In VHDL you can write something like this to set the "power-on" default condition for a signal

    Code:
    signal q : std_logic := '0'; -- power-on condition 
    signal rstN : std_logic := '1'; -- never asserts low
    
    process(clk, rstN)
    begin
      if (rstN = '0') then
          q <= '0';  -- never occurs
      elsif rising_edge(clk) then
          q <= d;
      end if;
    end process;
    Verilog will have a similar construct.

    Cheers,
    Dave

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    Default Re: Using PLL "lock" signal as the async reset in Verilog

    Quote Originally Posted by dwh@ovro.caltech.edu View Post
    If you use lock as an active-low reset, and it never goes high, then your logic will remain in reset.

    Conversely, if you have an active low reset signal, eg., rstN, and it never goes low, the reset condition will never occur. You will see this in simulation, in that a signal will never take on its reset value, but instead will take on the default value for the data type used in the process. In VHDL you can write something like this to set the "power-on" default condition for a signal

    Code:
    signal q : std_logic := '0'; -- power-on condition 
    signal rstN : std_logic := '1'; -- never asserts low
    
    process(clk, rstN)
    begin
      if (rstN = '0') then
          q <= '0';  -- never occurs
      elsif rising_edge(clk) then
          q <= d;
      end if;
    end process;
    Verilog will have a similar construct.

    Cheers,
    Dave

    It seems my statement "there is only low voltage level in "lock"" is confusing. "only low voltage" I mean is since after power on the FPGA, we will see the "lock" be low, then goes high later. So we will never see the lock signal has a falling edge if we don't reset the PLL.

    I think I should ask the question in another way. In Verilog, when I put the reset signal into the sensitive list, does Verilog really care is the reset edge or reset voltage level?

    I think it really cares is reset voltage level. This is because as you mentioned in VHDL, when we put the reset signal into the Process sensitive list, we even don't care whether is rising edge or falling edge.


    Thanks very much.

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    Default Re: Using PLL "lock" signal as the async reset in Verilog

    I also have the question about initial value for signal in VHDL.

    As you mentioned " signal q : std_logic := '0'; -- power-on condition ". Is this command synthesisable which make the signal q be "0" after power (don't need to do reset)? Or is this just for simulation?


    Thanks.

  9. #9
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    Default Re: Using PLL "lock" signal as the async reset in Verilog

    I mean is since after power on the FPGA, we will see the "lock" be low, then goes high later. So we will never see the lock signal has a falling edge if we don't reset the PLL.
    The negedge statement is so the Verilog understands you are using the signal as an asynchronous reset. It does not matter if there actually is a negedge.

    Is this command synthesisable which make the signal q be "0" after power (don't need to do reset)? Or is this just for simulation?
    This is synthesizeable - it tells the compiler what the initial register state is in the download bit-stream.

    Cheers,
    Dave

  10. #10
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    Default Re: Using PLL "lock" signal as the async reset in Verilog

    Quote Originally Posted by dwh@ovro.caltech.edu View Post
    The negedge statement is so the Verilog understands you are using the signal as an asynchronous reset. It does not matter if there actually is a negedge.


    This is synthesizeable - it tells the compiler what the initial register state is in the download bit-stream.

    Cheers,
    Dave
    Thanks very much, Dave.

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