I'm working on a Cyclone V, and I want to read and write into HPS's registers.
I have in QSys:
- One Nios II Processor (with on-chip memory, jtag-uart, system id, etc.)
- One HPS
- (and other components)
My Nios II processor act as a master and the HPS as a slave.
In Nios II:
I use IORD_32DIRECT, IOWR_32DIRECT, etc.
I watch signals thanks to signaltap (ARADDR, ARREADY, ARVALID, RLAST, RREADY, RVALID, BRESP, RRESP, RDATA, WDATA, etc.)
The document I used for address maps is the following : https://www.altera.com/en_US/pdfs/li...e-v/cv_5v4.pdf
Remarks and question:
I noticed that I could read/write in SDRAM-ACP registers (0x00000000 to 0xC0000000) and Lightweight H-to-F registers (from 0xFF200000 to 0xFF400000): page 423 of the document.
But what I want is to read/write at the address 0xFFC05000 which is the register for I2C1. The responses i get are BRESP and RRESP = 0x3 (which correspond to an error)
My question is : do I have something to active/enable if I want to access to these registers?