Results 1 to 5 of 5

Thread: Error 17044 in nios design with sdram

  1. #1
    Join Date
    May 2015
    Posts
    15
    Rep Power
    1

    Default Error 17044 in nios design with sdram

    Hi,

    I have built a design using Nios core and sdram (dd3 sdram controller with UniPHY). I get the following error during compilation:

    Error (17044): Illegal connection found on I/O input buffer primitive nios:inst|nios_sdram_new:sdram_new|nios_sdram_new_ p00|nios_sdram_new_p0_memphy:umemphy|nios_sdram_new_ p0_new_io_pads:uio_pads|nios_sdram_new_p0_altdqdqs :dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_stratixv:altdq_dqs2_inst |strobe_in. Source IO nios:inst|nios_sdram_new:sdram_new|nios_sdram_new_ p00|nios_sdram_new_p0_memphy:umemphy|nios_sdram_new_ p0_new_io_pads:uio_pads|nios_sdram_new_p0_altdqdqs :dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_stratixv:altdq_dqs2_inst |obuf_os_0 also drives out to other destination than the buffer.

    I am unable to understand why do I get this error?
    Can anybody help me out?

    Thanks.

  2. #2
    Join Date
    Mar 2013
    Location
    India
    Posts
    128
    Rep Power
    1

    Default Re: Error 17044 in nios design with sdram

    Hello,

    Carefully read last few words in error : "XXXX also drives out to other destination than the buffer." It suggests that one of your ports of sdram ( probably strobe_in ) has been connected to other logic besides to buffer. I think it should have connection only to buffer.

    I hope this will help.

    Cheers,
    Bhaumik

  3. #3
    Join Date
    May 2015
    Posts
    15
    Rep Power
    1

    Default Re: Error 17044 in nios design with sdram

    I dont think I have connected it wrongly. What are the correct connections to make? I just have two connections, the clock and reset. What connections are to be made for the sdram?

  4. #4
    Join Date
    May 2015
    Posts
    15
    Rep Power
    1

    Default Re: Error 17044 in nios design with sdram

    I read somewhere that running the pin_assignment.tcl script can sort this. But even this script is to run after a successful Analysis and Synthesis. But I cannot get past this error.
    Please help.

  5. #5
    Join Date
    Mar 2013
    Location
    India
    Posts
    128
    Rep Power
    1

    Default Re: Error 17044 in nios design with sdram

    Hello,

    Is it possible to upload your project here in archived form? I would like to have a look at it. To archive project, select Archive Project... under Project Tab.

    Cheers,
    Bhaumik

Similar Threads

  1. Nios II with enable Error-Correcting Code (ECC) (Qsys Design)
    By Remy ASTIER in forum General Discussion Forum
    Replies: 2
    Last Post: October 6th, 2015, 04:24 AM
  2. *Why* does analysis fail (err 17044) for some qsys + ddr projects?
    By TheoB in forum Quartus II and EDA Tools Discussion
    Replies: 8
    Last Post: June 12th, 2015, 08:55 AM
  3. DDR3 SDRAM Unimemphy issue with qsys design
    By hitesh_znz in forum IP Discussion
    Replies: 3
    Last Post: January 20th, 2014, 09:27 AM
  4. sopc design with ddr sdram controller
    By sasi.suyash in forum Quartus II and EDA Tools Discussion
    Replies: 3
    Last Post: April 5th, 2013, 10:33 AM
  5. Board design with ep3c25q240 and ddr1 sdram
    By SlashUU in forum General Altera Discussion
    Replies: 2
    Last Post: July 14th, 2011, 01:12 AM

Bookmarks

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •