First I want to say that I searched all the threads here, and while this is a common problem, I could not figure out how to solve it.
I am trying to use a small testbench I wrote using the Quartus testbench template writer, but I am getting this error:
Steps I took:
** Error: (vsim-3170) Could not find 'C:/Users/nettek/QuartusProjects/Final Project - 11.3.16 - par/test/simulation/modelsim/rtl_work.tb_test1'.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./Test_run_msim_rtl_vhdl.do PAUSED at line 14
1. Created a BDF file with two components in it, obviously it has input/output ports and some internal signals.
2. Created an HDL file from the BDF file. Added it to project. Removed the BDF file from project (did not delete it).
3. Created a testbench using the Quartus template writer.
4. Added the VHT file to project.
5. Took to Assignments -> Settings -> EDA tool settings -> Simulation ->
Chose compile test bench and chose the VHT file.
6. Tools -> Run simulation tool -> RTL simulation which opened Modelsim.
Of course I always made sure to compile whenever I needed to.
I don't understand this problem, just two days ago it didn't happen and now it does. What could be the problem?
Also, I would appreciate if you could tell me how to test internal signals of a BDF file in Modelsim using a testbench. I know that I can give the signals names, turn the BDF file into a HDL file and then compile it in Modelsim, and then force the signals, but I want to use a testbench to make this be automatic. Problem is, using a testbench, I only see the input/outputs.