I just met a problem about altera_pll on my cyclone V board. There is a 5CEFA4F23C8 FPGA on my board and the FPGA is conneted to a crystal oscillator via a clock input pin.
The crystal frequency is 50MHz and i want to generate an 100MHz signal but the output is nothing(zero).
I tested the reset signal and the crystal and found the reset is logic high(3.3V) and the crystal is 50MHz sine wave. Further more, I also tested the "locked" signal of the altera_pll and found it low.
Is there anyone who has met similar problem and can give me some advice?
Thanks a lot.