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Thread: How to generate Global RESET signal in Verilog?

  1. #11
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    Default Re: How to generate Global RESET signal in Verilog?

    "specify certain values on start" doesn't guarantee a predictable design state after the first clock edge, because the power-on-reset is released asynchronously and might cause timing violations. At worst case, a state machine might fall into a not-recoverable illegal state or a counter start at an unexpected arbitrary value.

    That's why you want a system wide reset that is synchronously released after the design clock is stable.

  2. #12
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    Default Re: How to generate Global RESET signal in Verilog?

    Quote Originally Posted by msj View Post
    In the top level, design a reset synchronizer which generates a synchronous reset signal. Connect that synchronized reset signal to your modules. A reset synchronizer should reset asynchronously, and set synchronously.
    There is no best way how to design the reset logic, however I also think that the above statement is a good practice.

    Thanks,
    Victor

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