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Thread: Pseudo Random Bit Sequence Verilog

  1. #1
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    Default Pseudo Random Bit Sequence Verilog

    Hi,

    I want to send a pseudo random bit sequence down a sfp+ port on my Stratix V fpga. Unfortunately I am unfamiliar with verilog. Can anyone help me with this or point me to the right resources? Thanks!

    UPDATE: I managed to compile this code. How can I test to see if it is doing what I want (ex. can I print the bit sequence somewhere?)

    module bit_generator(CLOCK_50, SFP);


    input CLOCK_50;
    output SFP;




    reg [6:0]d;
    always@(posedge CLOCK_50)
    begin
    d <= { d[5:0], d[6] ^ d[5] };
    end
    endmodule
    Last edited by SumeetB; October 6th, 2016 at 03:53 PM.

  2. #2
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    Default Re: Pseudo Random Bit Sequence Verilog

    Typically you would simulate the module. So your simulation would have to drive the CLOCK_50 which if you google around you'll find plenty of examples of how to do that. You would add CLOCK_50, SFP, and maybe the d register to the simulator waveform views so that you can watch it behave over time.

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    Default Re: Pseudo Random Bit Sequence Verilog

    Thanks for the reply. I prefer to test a physical implementation because I will be reusing the design of this basic implementation for testing an optical device. I've done some research and found that Quartus has megafunctions for instantiating SFP+ ports and the transceiver toolkit that automatically sends PRBS for BER testing. I have been trying to follow this example to get started: http://www.alterawiki.com/wiki/Strat...esign_Examples
    But some of the code confuses me. Perhaps you can help me understand how to implement something similar?

  4. #4
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    Default Re: Pseudo Random Bit Sequence Verilog

    I suspect there are also examples up on www.altera.com that cover the transceiver toolkit as well. Sorry I don't have any experience with transceivers so I don't know where to point you at. I think the PRBS pattern generation and checking might be implemented in the transceiver block so if you were looking for a code fragment for it you might not find it. If you want to see an example of a PRBS block you can take a look in the /ip directory in any of the zip files on this page: https://www.altera.com/support/suppo...n-example.html Those blocks might be overkill for what you are trying to do but they are programmable and can be setup by a system master like system console over JTAG, Nios II, HPS, etc...

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