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Thread: MegaWizard 2x8k Dual Port Memory

  1. #1
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    Default MegaWizard 2x8k Dual Port Memory

    Try to Convert a Project to Cyclone III but need Help with the Memory Type

    Orginal Code

    Code:
    module vidram(
                         output [7:0]	data_out,	// cpu interface		     input [7:0]    	data_in,
    		     input [10:0]   cpu_addr,
    		     input          	we,
                         output [7:0]	video_data,	// video hardware intf
                         input [10:0]	video_addr,
    		     input          	clk
    	     );
    
    
        // A single Spartan 8x2k 2-port RAM.  Easy.
        RAMB16_S9_S9
    	ram(.DIA(data_in),
                .DIPA(1'b0),
    	    .DOA(data_out),
                .DOPA(),
    	    .ADDRA(cpu_addr),
    	    .WEA(we),
    	    .ENA(1'b1),
    	    .SSRA(1'b0),
    	    .CLKA(~clk),	// see description
                .DIB(8'h00),
                .DIPB(1'b0),
                .DOB(video_data),
                .DOPB(),
                .ADDRB(video_addr),
                .WEB(1'b0),
                .ENB(1'b1),
                .SSRB(1'b0),
                .CLKB(~clk)		// see description
        );
             
    endmodule // vidram

    Mega Wizard generates me

    Code:
    module vidram (	clock,
    	data,
    	rdaddress,
    	wraddress,
    	wren,
    	q);
    
    
    	input	  clock;
    	input	[7:0]  data;
    	input	[10:0]  rdaddress;
    	input	[10:0]  wraddress;
    	input	  wren;
    	output	[7:0]  q;
    `ifndef ALTERA_RESERVED_QIS
    // synopsys translate_off
    `endif
    	tri1	  clock;
    	tri0	  wren;
    `ifndef ALTERA_RESERVED_QIS
    // synopsys translate_on
    `endif
    
    
    	wire [7:0] sub_wire0;
    	wire [7:0] q = sub_wire0[7:0];
    
    
    	altsyncram	altsyncram_component (
    				.address_a (wraddress),
    				.clock0 (clock),
    				.data_a (data),
    				.wren_a (wren),
    				.address_b (rdaddress),
    				.q_b (sub_wire0),
    				.aclr0 (1'b0),
    				.aclr1 (1'b0),
    				.addressstall_a (1'b0),
    				.addressstall_b (1'b0),
    				.byteena_a (1'b1),
    				.byteena_b (1'b1),
    				.clock1 (1'b1),
    				.clocken0 (1'b1),
    				.clocken1 (1'b1),
    				.clocken2 (1'b1),
    				.clocken3 (1'b1),
    				.data_b ({8{1'b1}}),
    				.eccstatus (),
    				.q_a (),
    				.rden_a (1'b1),
    				.rden_b (1'b1),
    				.wren_b (1'b0));
    	defparam
    		altsyncram_component.address_aclr_b = "NONE",
    		altsyncram_component.address_reg_b = "CLOCK0",
    		altsyncram_component.clock_enable_input_a = "BYPASS",
    		altsyncram_component.clock_enable_input_b = "BYPASS",
    		altsyncram_component.clock_enable_output_b = "BYPASS",
    		altsyncram_component.intended_device_family = "Cyclone III",
    		altsyncram_component.lpm_type = "altsyncram",
    		altsyncram_component.numwords_a = 2048,
    		altsyncram_component.numwords_b = 2048,
    		altsyncram_component.operation_mode = "DUAL_PORT",
    		altsyncram_component.outdata_aclr_b = "NONE",
    		altsyncram_component.outdata_reg_b = "CLOCK0",
    		altsyncram_component.power_up_uninitialized = "FALSE",
    		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
    		altsyncram_component.widthad_a = 11,
    		altsyncram_component.widthad_b = 11,
    		altsyncram_component.width_a = 8,
    		altsyncram_component.width_b = 8,
    		altsyncram_component.width_byteena_a = 1;
    
    
    
    
    endmodule
    but i need 2 Output Lines

  2. #2
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    Default Re: MegaWizard 2x8k Dual Port Memory

    You need to select "two read/write ports" on the very first MegaWizard page.

  3. #3
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    Default Re: MegaWizard 2x8k Dual Port Memory

    I had this idea already, but how do I have to assign

    orginal
    Code:
    module vidrama(
                         output [7:0]    data_out,    // cpu interface            
                         input [7:0]        data_in,
                         input [10:0]   cpu_addr,
                         input              we,
                         output [7:0]    video_data,    // video hardware intf
                         input [10:0]    video_addr,
                         input              clk
             );
    
    ....
    
    
    vidrama vidram(
    .data_out(vram_data),
    .data_in(data_in),
    .cpu_addr(addr[10:0]),
    .we(vram_we), 
    .video_addr(video_addr),
    .video_data(video_data),
    .clk(clk)
    );




    changed to

    Code:
    module vidrama (
        address_a,//cpu_addr,
        address_b,//video_addr,
        clock,//clk
        data_a,//data_in,
        data_b,//data_in,
        wren_a,//we,
        wren_b,//we,
        q_a,//data_out,
        q_b//video_data,
             );
    
    .....
    
    
        vidrama vidram(
                 .data_a(data_in),
                 .data_b(data_in),
                 .address_a,(addr[10:0]),
                 .address_b,(video_addr),
                 .wren_a(vram_we),   
                 .wren_b(vram_we),                             
                 .q_a(vram_data),
                 .q_b(video_data),
                 .clock(clk)
         );
    will not work
    Last edited by HarryPothead; November 21st, 2016 at 03:54 PM.

  4. #4
    Join Date
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    Default Re: MegaWizard 2x8k Dual Port Memory

    will not work
    No, why don't you copy the original port assignment, e.g. disable wren_b?

  5. #5
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    Default Re: MegaWizard 2x8k Dual Port Memory

    Sorry for German but my English is very Bad.

    Kannst du vielleicht bitte mal drüber schauen und mir den Weg zeigen ich bekomm es nicht hin


    Original Files
    http://www.share-online.biz/dl/WMW069HOT6M

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