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Thread: master_write_32 doesn't come out of master

  1. #1
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    Default master_write_32 doesn't come out of master

    I have instantiated a JTAG to MM Master block in my FPGA. I can attach to it from the system console and open it without problem.

    However, when I try to do a simple write:

    master_write_32 $path 0x0 0xdeadbeef

    It doesn't come out of the master according to signaltap.

    When I try to read it back:

    master_read_32 $path 0x0 1

    I get:

    0x000000ef. - only the low-order byte

    If I write multiple words, it still takes only that one byte and it doesn't send it out. I'm guessing that it's storing it internally.

    I thought maybe I needed some kind of slave in there, so I instantiated a (redundant) Slave to Master Bridge with full address map enabled and still get the same problem.

    Any ideas what could cause this?

    Thanks in advance.

  2. #2
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    Default Re: master_write_32 doesn't come out of master

    One issue was that I was using a master from the 5M chip rather than the Arria 10 on our board.

    That's because my master wasn't showing up with get_service_paths when I used the gui, even if I gave it the proper -device switch.

    Instead, what did work was using the command line:

    quartus_sh -s
    tcl> load_package systemconsole
    tcl> initialize_systemconsole
    tcl> get_service_paths master
    [all masters are shown. My showed up as .../phy_0/master]
    tcl> master_write ... - it worked

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