I'm a new player in the FPGA field and begun my journey with the DE0 board with Cyclone V SE.
I would appreciate if someone help me figure out the I2C routing inside this SoC. Here's the thing.
I'm using Qsys to develop my top-level entity. In my Qsys project I put the hard processor system block (HPS).
I right-click on the block, chose Edit, then select the Peripheral Pins tab. I scroll down to the I2C section and see four I2C controllers.
I read in the Cyclone V Device Handbook that the HPS provides four I2C controllers - so far so good. They can be configured as:
- FPGA (every controller) - I understand that the controller pins are routed to the FPGA,
- HPS I/O Set 0 (every controller) - I understand that the SDA/SCL pins are routed to the external pins A19 and C18 of the SoC (GPIO55 and GPIO56),
- HPS I/O Set 1 (controller 0 and 1) - I understand that the SDA/SCL pins are routed to the external pins A21 and K18 of the SoC (GPIO51 and GPIO52).
The DE0 board comes equipped with an ADXL345 on board connected to the I2C0 pins (hard wired to pins C18 and A19 of the SoC).
I have a Linux app that gets readings from the ADXL345 over I2C0 and prints them out on screen.
Here's the mind blower (at least for me):
No matter how I configure the I2C0 pins in Qsys (either as FPGA, HPS Set 0, HPS Set 1, or just leave them as GPIO's) the readings from the ADXL345 still get printed.
How is this possible? Is there some superior routing in the Soc that always connects the HPS I2C0 to the C18 and A19 pins, no matter how I configure it in Qsys?
It doesn't make much sense for me.
Please help me out with it.
Thanks in advance.