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Thread: Linux -> mSGDMA -> Dual Clock FIFO

  1. #1
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    Jul 2014
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    Default Linux -> mSGDMA -> Dual Clock FIFO

    For many weeks I am trying to transfer data(Mbytes) from HPS to FPGA but without success. I have DE1 SoC board and I use Linaro Linux from Altera site. My project is based on DE1_SOC_Linux_FB project from DE1-SoC_v.4.0.3_HWrevE_SystemCD. I would like with your help to make here some tutorial how to do it, step by step.

    My actual concept is to make mSGDMA with Memory-Mapped to Streaming mode and connect Dual clock FIFO. Output from FIFO i want export to my FPGA logic. I want to use dual clock FIFO because later I will be using SDRAM Controller. Is my concept ok?

    So, in first step I opened DE1_SOC_Linux_FB project, opened qSys, and upgraded IP to 15.1 version. Then I added mSGDMA, System and SDRAM Clocks for DE-series Boards and Avalon-ST Dual Clock FIFO. I connected clocks, resets, stream_source from mSGDMA to in signal in FIFO and exported output from FIFO. My first question is how to connect the rest of the signals and how to configure mSGDMA and FIFO? I attach the screen of my qSys connections.

    I will be very grateful for your responses. I have little time to do it

    Best wishes
    Attached Images Attached Images

  2. #2
    Join Date
    Jul 2014
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    Default Re: Linux -> mSGDMA -> Dual Clock FIFO

    I connected mm_read to f2h_axi_slave and csr and descriptor_slave to h2f_lw_axi_master. Is it good? I found similiar solution here: but data size is limited by on-chip memory(max 10 M. I need 64MB. How to send unlimited data size from linux memory to FIFO?
    Last edited by tomek160191; December 31st, 2016 at 03:54 AM.

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