Greetings everyone, I want to divide a 50 MHz clock frequency by (2,3,4,5,6,7,8). I am using a Block Diagram Schematics. Can I do this by using a (Counter)?? I have tried using the (modulus) but I don't get any output in the Simulation. What can I do please?? I have been using VHDL for a long time, but now I want to accomplish the task using Block Diagram/Schematics because I don't want to go back to the coding.
Your help means a lot to me, Thanks!