Greetings everyone, I want to design an 8x1 Multiplexing system. Starting with a frequency of (50 MHz) as the first input to the multiplexer; I want to divide this frequency by (2,3,...,8). What can I do to accomplish this task???? I am also using Block Diagram Schematics and I am sorry because I know this section of the forum is reserved for (VHDL) only. I suppose the coding is also good, but a little more difficult. So please help me I don't know what to do with my project. Can I use 4 PLLs and give each one a different frequency??? Thanks for your help.