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Thread: basic always block question

  1. #1
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    Default basic always block question

    I have questions about always blocks. Both will use the following always block for context:

    Code:
    always @ (posedge Clk)
    begin
    
    
    if (x1)
        q <= 1;
    else if (x2)
        q <= 0;
    else
        q <= q;
    
    
    end
    where q, x1 and x2 are all 1 bit wide.


    Would this code 'prioritize' checking x1 before x2? What would happen if x1 and x2 were both high?
    How exactly would it synthesize?

    Also, if I want q to retain it's value, is it necessary for me to explicitly code that in the form of q <= q? or is there another way?

    Thanks

  2. #2
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    Default Re: basic always block question

    Would this code 'prioritize' checking x1 before x2?
    Obviously yes.

    What would happen if x1 and x2 were both high?
    The same as only x1 high?

    How exactly would it synthesize?
    Any logic fulfilling the behavioral description would be correct. In FPGA as D-FF with preceding logic. You can watch the synthesis result in Quartus post synthesis net list.

    Also, if I want q to retain it's value, is it necessary for me to explicitly code that in the form of q <= q? or is there another way?
    The final else statement is redundant and can be omitted. A register keeps the previous state by default.

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