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Thread: Can't Simulate Buffer port in ModelSim

  1. #1
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    Default Can't Simulate Buffer port in ModelSim

    Hello everyone, I have the following simple VHDL code for clock frequency division:



    ---------------------- Frequency division using Variables -------------------
    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    -----------------------------------------
    ENTITY freq_divider IS
    PORT ( clk : IN STD_LOGIC;
    out2 : BUFFER STD_LOGIC);
    END freq_divider;
    -----------------------------------------
    ARCHITECTURE example OF freq_divider IS
    BEGIN
    PROCESS (clk)
    VARIABLE count2 : INTEGER RANGE 0 TO 7;
    BEGIN
    IF (clk'EVENT AND clk='0') THEN
    count2 := count2 + 1;
    IF (count2 = 3) THEN
    out2 <= NOT out2;
    count2 := 0;
    END IF;
    END IF;
    END PROCESS;
    END example;
    -----------------------------------------


    But when I try to Simulate it with ModelSim-Altera the (out2) signal does not give me any value. I was wondering is it because the port is assigned as (BUFFER)????? Please help me. Thanks

  2. #2
    Tricky is online now Moderator **Forum Master**
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    Default Re: Can't Simulate Buffer port in ModelSim

    Did you provide a clock on the clock port?

  3. #3
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    Default Re: Can't Simulate Buffer port in ModelSim

    Hi,

    with "does not give any value" I assume you mean 'U'? If so, it's because you never initialize "out2" to any value.

    Also, I agree with Tricky, you need a testbench that provides a clock. If you don't know about testbenches, Google has plenty of examples, e.g. here: https://www.doulos.com/knowhow/vhdl_...enches_part_1/.

    Best regards,
    GooGooCluster

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