Changing the HPS SDRAM PLL clock source from QSys
I'm in the early phases of design for a new board that will use a Cyclone V SE. I'm currently planning my clock domains for the HPS part and I see in several places in the Cyclone V HPS technical reference manual that the SDRAM PLL in the HPS can use three different clock sources: EOSC1, EOSC2, or a user clock from the FPGA (pages 2-3, 2-15, 2-65).
Now the problem is that I can't find how I can change this setting in QSys. I've instantiated an altera_hps component, and in the parameters > "HPS clocks", "Output clocks", I can define the clock source for the peripheral pll. In "Input clocks" I can enable or disable the FPGA to HPS Sdram reference clock, but I can't seem to find any setting to choose between ESOC1 or EOSC2.
Am I missing something? Where can I define this, or even know if the generated preloader will configure EOSC1 or EOSC2 as source for the Sdram Pll?
As a side question, does anyone have experience using a spread spectrum oscillator with a Soc FPGA? Obviously some I/O that require a precise clock frequency, such as Ethernet, can't use it. But what about the rest?
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