Hello guys, I have the following two projects. The first one Simulates perfectly inModelSim-Altera, but the second one does not show output. I want to know where is the problem in the second one??? By the way, both of them Simulate withQuartus II Simulator, but I want to use ModelSim-Altera Simulator because it is better. Of course, some might think that I must have done something wrong during the Simulation with ModelSim, but then I ask, how come the first design runs without problem?? I just give value to the clock and get the output perfectly. I really appreciate your help.

1st Design

--------------- Frequency division by 2 -----------------------------------`

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity freq_div_2 is

port(

clk : in STD_LOGIC;

out_clk2 : out STD_LOGIC

);

end freq_div_2;

architecture freq_div_2_arc of freq_div_2 is

begin

divider : process (clk) is

variable m : integer range 0 to 3 := 0;

variable n : std_logic := '0';

begin

if (falling_edge (clk)) then

m := m + 1;

if (m = 1) then

m := 0;

n := not n;

end if ;

end if;

out_clk2 <= n;

end process divider;

end freq_div_2_arc;

---------------------------------------------------------------------------------------------

2nd Design---------------------- Frequency division by 2 -------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

-----------------------------------------

ENTITY freq_div2 IS

PORT ( clk : IN STD_LOGIC;

out2 : BUFFER STD_LOGIC);

END freq_div2;

-----------------------------------------

ARCHITECTURE example OF freq_div2 IS

BEGIN

PROCESS (clk)

VARIABLE count2 : INTEGER RANGE 0 TO 7;

BEGIN

IF (clk'EVENT AND clk='0') THEN

count2 := count2 + 1;

IF (count2 = 1) THEN

out2 <= NOT out2;

count2 := 0;

END IF;

END IF;

END PROCESS;

END example;

-----------------------------------------

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