Results 1 to 2 of 2

Thread: How to properly connect PLL in Cyclone V?

  1. #1
    Join Date
    Nov 2016
    Rep Power

    Default How to properly connect PLL in Cyclone V?

    In my project I have a camera (three of them, actually) connected to FPGA. They are all driven by an external clock (CLK_48M). I need to generate reset (CAMERA_RESET_N) and trigger (CAMERA_TRIGGER) signals for the camera. To finetune the timing (all cams have the same frequency, but may require different command signals phase) I use PLL that generates clock to drive the signals. To make things more complicated the internal logic that drives reset and trigger is in another clock domain (dotted lines). I connected PLL, fixed the problems that I saw and now I am wondering if I didn't overdesign a bit.

    Here is what I do. I assume PLL's RESET signal can be in any clock domain, so I don't do anything there. I need PLL's LOCKED signal in camera's clock domain, so I sync it by three chained registers. In Altera PLL reference manuals they say that it takes up to 100 us until PLL locks and it can generate pulses on LOCKED signal during that time, so I delay the signal more (it's synchronized now, so I use counter, 100 us is 4800 periods of 48MHz clock). When the counter reaches its value I release camera from reset. Trigger synchronization is straightforward (three chained registers). The last thing is that I need to know when the PLL is ready (and if it fails), so I synchronize cameras RESET_N to my main clock domain (dotted).

    There are three cameras, so I will do the LOCKED signal synchronization (to generate CAMERA_RESET_N) for each of them. Same with TRIGGER. The READY signal is generated only once (I pick any clock).

    Is this how I am supposed to do it?
    Attached Images Attached Images

  2. #2
    Join Date
    Sep 2013
    Rep Power

    Default Re: How to properly connect PLL in Cyclone V?

    First and foremost, you need to do it in a way that works. You've clearly thought about the solution, it's very considered and thorough. Yes, synchronising signals and persisting them - especially when they take time to settle - is essential. There are plenty of ways to do this but they'll all fundamentally rely on counters. Providing you've the space in your device to do all this then fine (I don't see 'all this' being particularly big).

    Does it work? Does it fit? Does it meet timing? Answer those and you're heading in the right direction.


Similar Threads

  1. Cyclone-V SOC development kit not working properly
    By Ramamoorthy in forum FPGA, Hardcopy, and CPLD Discussion
    Replies: 2
    Last Post: March 10th, 2015, 09:57 AM
  2. cyclone II board not working properly
    By minhaz in forum Quartus II and EDA Tools Discussion
    Replies: 3
    Last Post: May 14th, 2012, 12:59 AM
  3. fast adc connect to cyclone ii
    By lgeorge123 in forum General Altera Discussion
    Replies: 3
    Last Post: March 6th, 2012, 02:57 PM
  4. How to connect two ddrs in a cyclone iii?
    By amey in forum General Altera Discussion
    Replies: 4
    Last Post: January 10th, 2010, 10:15 PM
  5. connect 2 PLLs in cyclone II
    By phithuc in forum Quartus II and EDA Tools Discussion
    Replies: 4
    Last Post: September 24th, 2008, 07:07 AM


Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts