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Thread: Expression has 32 elements ; expected 16

  1. #1
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    Default Expression has 32 elements ; expected 16

    Hi evryone !

    Plz help I have some problems in my modul, i get errors in : Line 71: Expression has 32 elements ; expected 16

    Line 47: Expression has 9 elements ; expected 16
    The tow lines :


    line 47 : wr <= curr_depth_bufbuf;
    line 71 : shift_p <= 2*shift_p;


    The declarations of generic and ports are the following with the signals also :

    generic (
    MAX_DEPTH : integer := 9; -- max tree depth
    HASH_LENGTH : integer := 2; -- hash length in words
    BLOCK_LENGTH : integer := 32; -- block length in words
    MEM_WIDTH : integer := 16); -- word width

    port (
    clk : in std_logic;
    rstb : in std_logic; -- active low async reset
    start : in std_logic; -- start bit
    path_depth : in std_logic_vector(MAX_DEPTH-1 downto 0); -- one hot
    w_beta : in std_logic_vector(MAX_DEPTH-1 downto 0); -- selected node;
    ptr : out std_logic_vector(MEM_WIDTH-1 downto 0); -- pointer value
    wr : out std_logic_vector(MEM_WIDTH-1 downto 0); -- enable ptr writre
    status : out std_logic); -- finish bit



    signal curr_depth, curr_depth_buf, curr_depth_bufbuf : std_logic_vector(MAX_DEPTH-1 downto 0);
    signal leftright, leftright_buf, status_tmp, leaf : std_logic; -- 1 is goto branch 1
    signal shift_w, shift_p, w_addr, p_addr : unsigned(MEM_WIDTH-1 downto 0);
    constant root_addr : integer := 2**MAX_DEPTH;

    Thank you

  2. #2
    Tricky is offline Moderator **Forum Master**
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    Default Re: Expression has 32 elements ; expected 16

    curr_depth_bufbuf has width 9, but wr has width 16.
    Simalarly for the other line

    you need to set the generics correctly or change the code so the widths match.

  3. #3
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    Default Re: Expression has 32 elements ; expected 16

    Thank you for your reply
    The other line is the same signal is a register that I multiply by 2
    shift_p <= 2*shift_p; error --> Expression has 32 elements ; expected 16
    His type is unsigned like you see !

  4. #4
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    Default Re: Expression has 32 elements ; expected 16

    Presumed you are using numeric_std library, the both errors can be fixed by writing:
    Code:
    shift_p <= shift_left(shift_p,1);
    -- or
    shift_p <= resize(2*shift_left,MEM_WIDTH);
    wr <= resize(curr_depth_bufbuf, MEM_WIDTH);
    In the first case, you have the problem, that the bit width of unsigned multiply increases the bit width. Resize cuts the additional bits on the left, necessary to assign the result to signal with fixed bit width.

    Similarly curr_depth_bufbuf must be zero filled on the left, resize can also do it. There are many other ways to achieve the same.

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    Default Re: Expression has 32 elements ; expected 16

    Yes, i am using numeric_std library

    Knowing that resize return UNSIGNED in the case of an unsigned argument

    After changing the code, I get this mistakes

    47: Expecting type std_logic_vector for <resize>.
    71: Formal <arg> has no actual or default value.

  6. #6
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    Default Re: Expression has 32 elements ; expected 16


    You will find enclosed my code file
    I have fixed these errors by passing from vector to unsigned but

    Here my process :
    Plz can you clarify me more about this process

    -- purpose: Compute shifts
    shift_proc: process (clk, start) is
    begin -- process
    if start = '0' then
    shift_p <= (others => '1');
    shift_w <= (others => '0');
    p_addr <= to_unsigned(root_addr, 16) + to_unsigned(hash_length, 16);
    elsif clk'event and clk = '1' then -- rising clock edge
    if leftright = leftright_buf then
    shift_p <= resize(2*shift_left, MEM_WIDTH);
    shift_w <= shift_w + shift_p;
    else
    shift_w <= resize(2*shift_left, MEM_WIDTH);
    shift_p <= shift_w + shift_p;
    end if;
    p_addr <= p_addr - shift_p*hash_length;
    if leaf='0' then
    w_addr <= p_addr - shift_w*hash_length;
    else
    w_addr <= p_addr - (unsigned(w_beta)/2)*hash_length - (shift_w-(unsigned(w_beta)/2))*block_length;
    end if;
    end if;
    end process;


    p_addr <= p_addr - shift_p*hash_length;
    w_addr <= p_addr - shift_w*hash_length;
    w_addr <= p_addr - (unsigned(w_beta)/2)*hash_length - (shift_w-(unsigned(w_beta)/2))*block_length;
    Attached Files Attached Files
    Last edited by Sfato; January 25th, 2017 at 12:09 AM.

  7. #7
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    Default Re: Expression has 32 elements ; expected 16

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    --use ieee.std_logic_unsigned.all;


    entity witness is

    generic (
    MAX_DEPTH : integer := 9; -- max tree depth
    HASH_LENGTH : integer := 2; -- hash length in words
    BLOCK_LENGTH : integer := 32; -- block length in words
    MEM_WIDTH : integer := 16); -- word width


    port (
    clk : in std_logic;
    rstb : in std_logic; -- active low async reset
    start : in std_logic; -- start bit
    path_depth : in std_logic_vector(MAX_DEPTH-1 downto 0); -- one hot
    w_beta : in std_logic_vector(MAX_DEPTH-1 downto 0); -- selected node;
    ptr : out std_logic_vector(MEM_WIDTH-1 downto 0); -- pointer value
    wr : out std_logic_vector(MEM_WIDTH-1 downto 0); -- enable ptr writre
    status : out std_logic); -- finish bit


    end entity witness;


    architecture arch of witness is
    signal curr_depth, curr_depth_buf, curr_depth_bufbuf : unsigned(MAX_DEPTH-1 downto 0);
    signal leftright, leftright_buf, status_tmp, leaf : std_logic; -- 1 is goto branch 1
    signal shift_w, shift_p, w_addr, p_addr : unsigned(MEM_WIDTH-1 downto 0);
    constant root_addr : integer := 2**(MAX_DEPTH)-1;

    begin -- architecture arch


    -- purpose: Buffer some signals
    buf: process (clk, rstb) is
    begin -- process buf
    if clk'event and clk = '1' then -- rising clock edge
    curr_depth_bufbuf <= curr_depth_buf;
    curr_depth_buf <= curr_depth;
    leftright_buf <= leftright;
    end if;
    end process buf;


    leftright <= '0' when (unsigned(w_beta) and curr_depth) = (9 downto 0 => '0') else '1'; --bitwise
    leaf <= path_depth(MAX_DEPTH-1) and curr_depth_buf(0);
    ptr <= std_logic_vector(w_addr);
    wr <= std_logic_vector(resize(curr_depth_bufbuf, MEM_WIDTH));


    -- purpose: shift current depth
    -- type : sequential
    shift_depth: process (clk, rstb) is
    begin -- process shift_depth
    if clk'event and clk = '1' then -- rising clock edge
    if start = '0' then
    curr_depth <= unsigned(path_depth);
    else
    curr_depth <= '0' & curr_depth(MAX_DEPTH-1 downto 1); --which level we are in the tree
    end if;
    end if;
    end process shift_depth;


    -- purpose: Compute shifts
    shift_proc: process (clk, start) is
    begin -- process
    if start = '0' then
    shift_p <= (others => '1');
    shift_w <= (others => '0');
    p_addr <= to_unsigned(root_addr, 16) + to_unsigned(hash_length, 16);
    elsif clk'event and clk = '1' then -- rising clock edge
    if leftright = leftright_buf then
    shift_p <= resize(2*shift_left, MEM_WIDTH);
    shift_w <= shift_w + shift_p;
    else
    shift_w <= resize(2*shift_left, MEM_WIDTH);
    shift_p <= shift_w + shift_p;
    end if;
    p_addr <= p_addr - shift_p*hash_length;
    if leaf='0' then
    w_addr <= p_addr - shift_w*hash_length;
    else
    w_addr <= p_addr - (unsigned(w_beta)/2)*hash_length - (shift_w-(unsigned(w_beta)/2))*block_length;
    end if;
    end if;
    end process;





    -- purpose: Handle status bit
    status_proc: process (clk, rstb) is
    begin -- process status_proc
    if rstb = '0' then -- asynchronous reset (active low)
    status_tmp <= '0';
    elsif clk'event and clk = '1' then -- rising clock edge
    status_tmp <= status_tmp or curr_depth_bufbuf(0);
    end if;
    end process status_proc;
    status <= status_tmp;
    end architecture arch;

    here is my code can plz clarify me more about the process "compute shift"

  8. #8
    Tricky is offline Moderator **Forum Master**
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    Default Re: Expression has 32 elements ; expected 16

    What exactly do you need clarifying?

  9. #9
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    Default Re: Expression has 32 elements ; expected 16

    For example, for this registres.

    what does it mean when we do this In terms of movement of bit :

    shift_p <= 2*shift_left; or shift_w <= shift_w + shift_p;
    this also
    p_addr <= p_addr - shift_p*hash_length;

  10. #10
    Tricky is offline Moderator **Forum Master**
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    Default Re: Expression has 32 elements ; expected 16

    multiplying a number by 2^N shifts a number to the left by N bits.

    The second line is just a normal subtract.

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