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Thread: SignalTap II issue

  1. #11
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    Default Re: SignalTap II issue

    Quote Originally Posted by sstrell View Post
    As mentioned, use false paths for switches and LEDs. altera_reserved_tck is the JTAG clock. You don't need to constrain this.
    Hello,
    Here is the last version of .SDC file (if I correctly understood the suggestion):
    Code:
    create_clock -name clk -period 20.000 [get_ports {clk}]derive_clock_uncertainty
    #set_input_delay -clock { clk } 5 [get_ports {clr_b}]
    #set_input_delay -clock { clk } 5 [get_ports {reset_b}]
    #set_input_delay -clock { clk } 5 [get_ports {sw}]
    
    
    set_false_path -from [get_ports {clr_b}]
    set_false_path -from [get_ports {reset_b}]
    set_false_path -from [get_ports {sw}]
    Unfortunately it didn't help: input signal on sw port puts the "state machine" in undefined state.
    Moreover, there are still unconstrained inputs ... is it correct ? In this design there are 4 inputs (2 buttons, 1 switch, 1 clock) and all input ports are present in .SDC.


    Are there some options that I could add into .SDC file in order to proceed with full timing analysis ?

    Concerning metastability issue, that could be the cause of problem, I have a couple of questions:
    1. How to properly setup "Report Metastability" in TimeQuest in order to get reliable overview of metastability issues. Actually when I run "Report Metastability", the "non-calculated" value is filled everywhere in the report
    2. The metastability issue can be only managed with "design-related" means (e.g. add synchronization flip-flops in the verilog-coded module just after input ports, and then apply thy synchronizer outputs to state machine) or there are some options in Quartus, that allow to do it automatically (e.g. specify in some way a particular input port as port that requires synchronization). In this regard Assignment Editor could be evoked: the Assignment Name column has a collection of different values, including, for example, Synchronizer Identification. So, resuming ... the synchronization chain can be added only in VHDL/Verilog or also via some option in Assignment Editor ?

    Thanks
    Attached Images Attached Images

  2. #12
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    Default Re: SignalTap II issue

    Moreover, there are still unconstrained inputs ... is it correct ? In this design there are 4 inputs (2 buttons, 1 switch, 1 clock) and all input ports are present in .SDC.
    Run "Report Ignored Constraints" command in TimeQuest to see if all your SDC commands are accepted.
    After running "Report Unconstrained Paths" check which actual ports are unconstrained (In Report window see Unconstrained Paths -> Setup Analysis -> Unconstrained Input Ports or Unconstrained Output Ports). This way you will find out which ports are left unconstrained or there is some error in your SDC file.

    I am guesing that you will find that those two input ports are altera_reserved_tdi and altera_reserved_tms. You can also use set_false_path for those ports. For JTAG i use:

    create_clock -period "10 MHz" -name altera_reserved_tck [get_ports altera_reserved_tck]
    set_false_path -from [get_ports {altera_reserved_tdi}]
    set_false_path -from [get_ports {altera_reserved_tms}]
    set_false_path -to [get_ports {altera_reserved_tdo}]
    # Specify the JTAG clock in a group
    set_clock_groups -asynchronous -group altera_reserved_tck

    How to properly setup "Report Metastability" in TimeQuest in order to get reliable overview of metastability issues. Actually when I run "Report Metastability", the "non-calculated" value is filled everywhere in the report
    I think you have to set Synchronizer identification option to AUTO in Settings -> TimeQuest Timing Analyzer.

    The metastability issue can be only managed with "design-related" means (e.g. add synchronization flip-flops in the verilog-coded module just after input ports, and then apply thy synchronizer outputs to state machine) or there are some options in Quartus, that allow to do it automatically (e.g. specify in some way a particular input port as port that requires synchronization). In this regard Assignment Editor could be evoked: the Assignment Name column has a collection of different values, including, for example, Synchronizer Identification. So, resuming ... the synchronization chain can be added only in VHDL/Verilog or also via some option in Assignment Editor ?
    Yes synchronization chain can be added only in VHDL/Verilog. Synchronizer Identification option prevents synchronization chain from optimizations and enables MTBF analysis.

  3. #13
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    Default Re: SignalTap II issue

    Quote Originally Posted by vlrean View Post
    Run "Report Ignored Constraints" command in TimeQuest to see if all your SDC commands are accepted.
    After running "Report Unconstrained Paths" check which actual ports are unconstrained (In Report window see Unconstrained Paths -> Setup Analysis -> Unconstrained Input Ports or Unconstrained Output Ports). This way you will find out which ports are left unconstrained or there is some error in your SDC file.

    I am guesing that you will find that those two input ports are altera_reserved_tdi and altera_reserved_tms. You can also use set_false_path for those ports. For JTAG i use:

    create_clock -period "10 MHz" -name altera_reserved_tck [get_ports altera_reserved_tck]
    set_false_path -from [get_ports {altera_reserved_tdi}]
    set_false_path -from [get_ports {altera_reserved_tms}]
    set_false_path -to [get_ports {altera_reserved_tdo}]
    # Specify the JTAG clock in a group
    set_clock_groups -asynchronous -group altera_reserved_tck
    Yes, it's the case, the unconstraiuned inputs are altera_reserved_tdi and altera_reserved_tms.
    Concerning constraints for JTAG signals is it necessary to create altera reserved_clk, as it's already present ?
    timequest_clocks_report.JPG
    Thanks

  4. #14
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    Default Re: SignalTap II issue

    I think you have to set Synchronizer identification option to AUTO in Settings -> TimeQuest Timing Analyzer.
    I've checked ... this option is set to AUTO, but metastability values still aren't calculated

    Metastability_Report.JPG

  5. #15
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    Default Re: SignalTap II issue

    Finally, Synchronization Register Chains resolved the problem.
    I applied 2 flip-flops to sw input:
    Code:
    	reg sw1, sw2;
    	
    	DFF sync1 (.d(sw), .clk(clk), .clrn(1'b1), .prn(1'b1), .q(sw1));
    	DFF sync2 (.d(sw1), .clk(clk), .clrn(1'b1), .prn(1'b1), .q(sw2));
    and then applied sw2 to state machine (instead of sw).
    However the signals sw1 and sw2 aren't accessible in SignalTap ... only sync1, sync2.
    I suppose that sync1 and sync2 are actually sw1 and sw2 ?

    SignalTap.JPG

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