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Thread: MAX FPGA/CPLD capable of dynamic signal shifting, 3.3v -> 1.8v on same GPIO?

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    Default MAX FPGA/CPLD capable of dynamic signal shifting, 3.3v -> 1.8v on same GPIO?

    Wondering if the MAX series 10 FPGA or 5 CPLD are capable of dynamic signal shifting on the same GPIO. Ex. signaling at 3.3v for initialization and then switching to 1.8v for data transfer?

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    Default Re: MAX FPGA/CPLD capable of dynamic signal shifting, 3.3v -> 1.8v on same GPIO?

    Are you proposing to change the voltage at which the I/O bank in question is powered after initialization, before data transfer? Unusual, but I don't see why it won't work.

    You can't really do so without changing the voltage. The MAX device can't drive out at a 1.8V I/O standard if the I/O bank is powered at 3.3V (and vice versa). Driving a 3.3V signal into a 1.8V powered bank is probably not acceptable either - check the datasheet. From memory, you can drive a 3.3V signal into a 2.5V powered bank, but not if it's powered at a lower voltage.

    Assuming scenario 1, the only* issue I can think of is timing analysis, which Quartus will only do based on one set of I/O signalling standards. So, you'll be operating, in part at least, out of spec. This may not matter. Perhaps your initialization is slow enough such that constraining your design for your data transfer mode of operating is adequate.

    You'll also have to be careful how you change the voltage on the bank. Check that the bank in question isn't included n the FPGA's POR state machine. Bad behaviour on such a bank's voltage could cause your device to reset.

    * there may be other issues...

    Cheers,
    Alex

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    Default Re: MAX FPGA/CPLD capable of dynamic signal shifting, 3.3v -> 1.8v on same GPIO?

    Quote Originally Posted by a_x_h_75 View Post
    Are you proposing to change the voltage at which the I/O bank in question is powered after initialization, before data transfer? Unusual, but I don't see why it won't work.

    You can't really do so without changing the voltage. The MAX device can't drive out at a 1.8V I/O standard if the I/O bank is powered at 3.3V (and vice versa). Driving a 3.3V signal into a 1.8V powered bank is probably not acceptable either - check the datasheet. From memory, you can drive a 3.3V signal into a 2.5V powered bank, but not if it's powered at a lower voltage.

    Assuming scenario 1, the only* issue I can think of is timing analysis, which Quartus will only do based on one set of I/O signalling standards. So, you'll be operating, in part at least, out of spec. This may not matter. Perhaps your initialization is slow enough such that constraining your design for your data transfer mode of operating is adequate.

    You'll also have to be careful how you change the voltage on the bank. Check that the bank in question isn't included n the FPGA's POR state machine. Bad behaviour on such a bank's voltage could cause your device to reset.

    * there may be other issues...

    Cheers,
    Alex
    Thank you. I read the Altera MAX Series as Voltage Level Shifters application note (https://www.altera.com/en_US/pdfs/li...e/an/an490.pdf) and it says it supports multiple different i/O voltage on different I/O banks. Would it be better to have two I/O banks connected in parallel to the output and switch between the two? This is what I'm working on btw: http://www.alteraforum.com/forum/showthread.php?t=54866

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    Default Re: MAX FPGA/CPLD capable of dynamic signal shifting, 3.3v -> 1.8v on same GPIO?

    It seems the forums ate my post.. not sure whats going on.

    Quote Originally Posted by a_x_h_75 View Post
    Are you proposing to change the voltage at which the I/O bank in question is powered after initialization, before data transfer? Unusual, but I don't see why it won't work.

    You can't really do so without changing the voltage. The MAX device can't drive out at a 1.8V I/O standard if the I/O bank is powered at 3.3V (and vice versa). Driving a 3.3V signal into a 1.8V powered bank is probably not acceptable either - check the datasheet. From memory, you can drive a 3.3V signal into a 2.5V powered bank, but not if it's powered at a lower voltage.

    Assuming scenario 1, the only* issue I can think of is timing analysis, which Quartus will only do based on one set of I/O signalling standards. So, you'll be operating, in part at least, out of spec. This may not matter. Perhaps your initialization is slow enough such that constraining your design for your data transfer mode of operating is adequate.

    You'll also have to be careful how you change the voltage on the bank. Check that the bank in question isn't included n the FPGA's POR state machine. Bad behaviour on such a bank's voltage could cause your device to reset.

    * there may be other issues...

    Cheers,
    Alex
    Thank you!

    I read this application note Altera MAX Series as Voltage Level Shifters (https://www.altera.com/en_US/pdfs/li...e/an/an490.pdf) and it says the MAX 10 can output different voltage signals on different I/O banks - would it be better to have two I/O banks connected in series with a diode to switch from 3.3v to 1.8v after initialization? (Btw.. it is for this project http://www.alteraforum.com/forum/showthread.php?t=54866)

    Alternatively, I think this could be done in an FPGA and that might save an re-spins or patch wires.. thats probably the better solution though more expensive up front.

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    Default Re: MAX FPGA/CPLD capable of dynamic signal shifting, 3.3v -> 1.8v on same GPIO?

    The forum deletes my post every time I try to link a related post.. not sure why..

    Quote Originally Posted by a_x_h_75 View Post
    Are you proposing to change the voltage at which the I/O bank in question is powered after initialization, before data transfer? Unusual, but I don't see why it won't work.

    You can't really do so without changing the voltage. The MAX device can't drive out at a 1.8V I/O standard if the I/O bank is powered at 3.3V (and vice versa). Driving a 3.3V signal into a 1.8V powered bank is probably not acceptable either - check the datasheet. From memory, you can drive a 3.3V signal into a 2.5V powered bank, but not if it's powered at a lower voltage.

    Assuming scenario 1, the only* issue I can think of is timing analysis, which Quartus will only do based on one set of I/O signalling standards. So, you'll be operating, in part at least, out of spec. This may not matter. Perhaps your initialization is slow enough such that constraining your design for your data transfer mode of operating is adequate.

    You'll also have to be careful how you change the voltage on the bank. Check that the bank in question isn't included n the FPGA's POR state machine. Bad behaviour on such a bank's voltage could cause your device to reset.

    * there may be other issues...

    Cheers,
    Alex
    Thank you!

    I read this application note Altera MAX Series as Voltage Level Shifters (https://www.altera.com/en_US/pdfs/li...e/an/an490.pdf) and it says the MAX 10 can output different voltage signals on different I/O banks - would it be better to have two I/O banks connected in parallel with a diode to the interface? That way I can switch voltage levels from 3.3v -> 1.8v after initialization without resetting the chip or messing with the system voltages that are setup and seems to be within the spec of the tools. (Btw.. it is for this project alteraforum.com/forum/showthread.php?t=54866 )

    Alternatively, I think this could be done in an FPGA and that might save an re-spins or patch wires.. thats probably the better solution though more expensive up front.
    Last edited by e97; February 17th, 2017 at 12:05 AM.

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    Default Re: MAX FPGA/CPLD capable of dynamic signal shifting, 3.3v -> 1.8v on same GPIO?

    would it be better to have two I/O banks connected in parallel with a diode to the interface?
    No diodes, just parallel a 1.8 and 3.3V driver. Take care that one driver is three-stated when the other is driving out.

    Finally, if you don't need high speed, you can either use a single 1.8V driver with pull-up to 3.3V or vice versa. Three-stating the output activates the pull-up level.

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