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Thread: FPGA-to-HPS Bridges Design Example

  1. #1
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    Jun 2017
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    Default FPGA-to-HPS Bridges Design Example

    I am looking at the FPGA-to-HPS Bridges Design Example in Altera website, I downloaded the project for Cyclone V SoC, and opened the hps_system.qsys, there is a component, AXI Cache Secruity Bridge, I can not find document for this bridge, anyone know what it is for? Thanks......

  2. #2
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    Nov 2017
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    Default Re: FPGA-to-HPS Bridges Design Example


    It is a custom IP, you can see the Verilog code given in directory "CV_FPGA_to_HPS_Bridge_Design_Example\ip\axi_cache _secruity_bridge".
    For more information read the commented lines in .v file and link below.

    Best Regards,
    Anand Raj Shankar
    (This message was posted on behalf of Intel Corporation)
    Last edited by Anand Raj Shankar; April 22nd, 2018 at 09:09 PM.

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