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Thread: Constraining LEDs/Switches to VHDL onDE1-SoC

  1. #1
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    Default Constraining LEDs/Switches to VHDL onDE1-SoC

    Hello, I am trying to write some basic VHDL that "slide" an on led down the 10 leds on the DE1-SoC board. I have loaded the .sof onto the board but nothing is lighting up. I think the VHDL is good because I have compiled and loaded it onto a Xilinx board. I am guessing the issue is with the .sdc or .qsf files which I am given to understand constrain the code to the on-board hardware. I will post the VHDL, the .sdc, and the .qsf.

    led_slide.vhd
    Code:
    library ieee;use ieee.std_logic_1164.all;
    
    
    entity led_slide is
      port(
        clk:    in std_logic;
        sel:    in std_logic;
        z:        out std_logic_vector(9 downto 0)
      );
    end led_slide;
    
    
    architecture Behavioral of led_slide is
      type my_state is (
        s0,
        s1,
        s2,
        s3,
        s4,
        s5,
        s6,
        s7,
        s8,
        s9
      );
      signal n_s: my_state;
      signal clk_div:    std_logic;
    begin
      process(clk_div)
      begin 
        if clk_div='1' and clk_div'event then
          case n_s is
            when s0 =>
              z <= "1000000000";
              if sel='1' then
                  n_s <= s1;
              else
                  n_s <= s9;
              end if;
            when s1 =>
              z <= "0100000000";
              if sel='1' then
                  n_s <= s2;
              else
                  n_s <= s1;
              end if;
            when s2 =>
              z <= "0010000000";
              if sel='1' then
                  n_s <= s3;
              else
                  n_s <= s1;
              end if;
            when s3 =>
              z <= "0001000000";
              if sel='1' then
                  n_s <= s4;
              else
                  n_s <= s2;
              end if;
            when s4 =>
              z <= "0000100000";
              if sel='1' then
                  n_s <= s5;
              else
                  n_s <= s3;
              end if;
            when s5 =>
              z <= "0000010000";
              if sel='1' then
                  n_s <= s6;
              else
                  n_s <= s4;
              end if;
            when s6 =>
              z <= "0000001000";
              if sel='1' then
                  n_s <= s7;
              else
                  n_s <= s5;
              end if;
            when s7 =>
              z <= "0000000100";
              if sel='1' then
                  n_s <= s8;
              else
                  n_s <= s6;
              end if;
            when s8 =>
              z <= "0000000010";
              if sel='1' then
                  n_s <= s9;
              else
                  n_s <= s7;
              end if;
            when s9 =>
              z <= "0000000001";
              if sel='1' then
                  n_s <= s0;
              else
                  n_s <= s8;
              end if;
          end case;
        end if;
      end process;
    
    
      process(clk)
        variable count: integer;
      begin
        if clk='1' and clk'event then
           if count=99999 then
              clk_div <= not clk_div;
              count := 0;
           else
              count := count + 1;
           end if;
        end if;
      end process;
    end Behavioral;
    de1soc_master.qsf
    Code:
    set_global_assignment -name FAMILY "Cyclone V"
    set_global_assignment -name DEVICE 5CSEMA5F31C6
    set_global_assignment -name TOP_LEVEL_ENTITY "DE1_SoC"
    set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
    set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
    set_global_assignment -name SDC_FILE led_slide.sdc
    
    ##============================================================
    ## LEDR
    ##============================================================
    set_location_assignment PIN_V16 -to z[0]
    set_location_assignment PIN_W16 -to z[1]
    set_location_assignment PIN_V17 -to z[2]
    set_location_assignment PIN_V18 -to z[3]
    set_location_assignment PIN_W17 -to z[4]
    set_location_assignment PIN_W19 -to z[5]
    set_location_assignment PIN_Y19 -to z[6]
    set_location_assignment PIN_W20 -to z[7]
    set_location_assignment PIN_W21 -to z[8]
    set_location_assignment PIN_Y21 -to z[9]
    set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z[0]
    set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z[1]
    set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z[2]
    set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z[3]
    set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z[4]
    set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z[5]
    set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z[6]
    set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z[7]
    set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z[8]
    set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to z[9]
    #
    led_slide.sdc
    Code:
    #**************************************************************
    # Altera DE1-SoC SDC settings
    # Users are recommended to modify this file to match users logic.
    #**************************************************************
    
    
    #**************************************************************
    # Create Clock
    #**************************************************************
    create_clock -period 20 [get_ports CLOCK_50]
    create_clock -period 20 [get_ports CLOCK2_50]
    create_clock -period 20 [get_ports CLOCK3_50]
    create_clock -period 20 [get_ports CLOCK4_50]
    
    
    create_clock -period "27 MHz"  -name tv_27m [get_ports TD_CLK27]
    
    # VGA : 640x480@60Hz
    create_clock -period "25.18 MHz" -name clk_vga [get_ports VGA_CLK]
    
    #**************************************************************
    # Create Generated Clock
    #**************************************************************
    derive_pll_clocks
    
    
    #**************************************************************
    # Set Clock Uncertainty
    #**************************************************************
    derive_clock_uncertainty
    
    #**************************************************************
    # Set Input Delay
    #**************************************************************
    # Board Delay (Data) + Propagation Delay - Board Delay (Clock)
    set_input_delay -max -clock clk_dram -0.048 [get_ports DRAM_DQ*]
    set_input_delay -min -clock clk_dram -0.057 [get_ports DRAM_DQ*]
    
    
    set_input_delay -max -clock tv_27m 3.692 [get_ports TD_DATA*]
    set_input_delay -min -clock tv_27m 2.492 [get_ports TD_DATA*]
    set_input_delay -max -clock tv_27m 3.654 [get_ports TD_HS]
    set_input_delay -min -clock tv_27m 2.454 [get_ports TD_HS]
    set_input_delay -max -clock tv_27m 3.656 [get_ports TD_VS]
    set_input_delay -min -clock tv_27m 2.456 [get_ports TD_VS]
    
    
    #**************************************************************
    # Set Output Delay
    #**************************************************************
    # max : Board Delay (Data) - Board Delay (Clock) + tsu (External Device)
    # min : Board Delay (Data) - Board Delay (Clock) - th (External Device)
    set_output_delay -max -clock clk_dram 1.452  [get_ports DRAM_DQ*]
    set_output_delay -min -clock clk_dram -0.857 [get_ports DRAM_DQ*]
    set_output_delay -max -clock clk_dram 1.531 [get_ports DRAM_ADDR*]
    set_output_delay -min -clock clk_dram -0.805 [get_ports DRAM_ADDR*]
    set_output_delay -max -clock clk_dram 1.533  [get_ports DRAM_*DQM]
    set_output_delay -min -clock clk_dram -0.805 [get_ports DRAM_*DQM]
    set_output_delay -max -clock clk_dram 1.510  [get_ports DRAM_BA*]
    set_output_delay -min -clock clk_dram -0.800 [get_ports DRAM_BA*]
    set_output_delay -max -clock clk_dram 1.520  [get_ports DRAM_RAS_N]
    set_output_delay -min -clock clk_dram -0.780 [get_ports DRAM_RAS_N]
    set_output_delay -max -clock clk_dram 1.5000  [get_ports DRAM_CAS_N]
    set_output_delay -min -clock clk_dram -0.800 [get_ports DRAM_CAS_N]
    set_output_delay -max -clock clk_dram 1.545 [get_ports DRAM_WE_N]
    set_output_delay -min -clock clk_dram -0.755 [get_ports DRAM_WE_N]
    set_output_delay -max -clock clk_dram 1.496  [get_ports DRAM_CKE]
    set_output_delay -min -clock clk_dram -0.804 [get_ports DRAM_CKE]
    set_output_delay -max -clock clk_dram 1.508  [get_ports DRAM_CS_N]
    set_output_delay -min -clock clk_dram -0.792 [get_ports DRAM_CS_N]
    
    
    set_output_delay -max -clock clk_vga 0.220 [get_ports VGA_R*]
    set_output_delay -min -clock clk_vga -1.506 [get_ports VGA_R*]
    set_output_delay -max -clock clk_vga 0.212 [get_ports VGA_G*]
    set_output_delay -min -clock clk_vga -1.519 [get_ports VGA_G*]
    set_output_delay -max -clock clk_vga 0.264 [get_ports VGA_B*]
    set_output_delay -min -clock clk_vga -1.519 [get_ports VGA_B*]
    set_output_delay -max -clock clk_vga 0.215 [get_ports VGA_BLANK]
    set_output_delay -min -clock clk_vga -1.485 [get_ports VGA_BLANK]
    Last edited by jackfrye11; May 5th, 2018 at 03:09 PM.

  2. #2
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    Default Re: Constraining LEDs/Switches to VHDL onDE1-SoC

    It is clearly a problem with the constraints
    fail2.jpg
    fail.jpg
    It is clear my qsf is reading the sdc because if I mess with the .sdc, it will fail to compile. I am not sure how to create and connect my VHDL clk input to a real clk

    Here are the critical warnings I am seeing
    fail3.jpg

  3. #3
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    Default Re: Constraining LEDs/Switches to VHDL onDE1-SoC

    Hi,

    I have loaded the .sof onto the board but nothing is lighting up

    You have already answered your own question.
    I am not sure how to create and connect my VHDL clk input to a real clk
    Without clock your module will not work. Create top module with board pin names and create instance of your own module and connect board pins with your module.

  4. #4
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    Default Re: Constraining LEDs/Switches to VHDL onDE1-SoC

    I was able to constrain the VHDL clk, but now the tool says clk_div is unconstrained which I do not understand because it is just a clock generated based on the count of a register that is iterated by the tick of clk. Do I have to write a constraint in the sdc for this clock as well?



    In de1soc_master.qsf
    set_global_assignment -name FAMILY "Cyclone V"
    set_global_assignment -name DEVICE 5CSEMA5F31C6
    set_global_assignment -name TOP_LEVEL_ENTITY "DE1_SoC"
    set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
    set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
    set_global_assignment -name clk_gen.sdc
    #set_global_assignment -name SDC_FILE DE1_SoC.sdc

    New constraint clk_gen.sdc
    create_clock -period 20 [get_ports clk]
    Attached Images Attached Images

  5. #5
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    Default Re: Constraining LEDs/Switches to VHDL onDE1-SoC

    Forget about sdc for a while. It's surely not your problem. But you absolutely need a pin assignment for the clock input.

    Pin assignments can be comfortably entered and checked in the Pin Planner tool. Another option is to start your design using an example shipped with your DE1 board, it already has useful pin assignments for all development board signals.

  6. #6
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    Default Re: Constraining LEDs/Switches to VHDL onDE1-SoC

    I think you are mixing the purpose of .qsf assignments and .sdc constrains. Have you assigned clk to actual FPGA pin location and actual clk source? For now use Pin Planner from Quartus to assign actual FPGA pins to your top level ports, assign clk port to FPGA pin where is some clock source is connected (e.g oscillator).

    After you assign pin locations your design should work (if your VHDL is good enough), even if Timequest will tell you that your design does not meet timing because tool will assume that you are running your design at 1GHz clock frequency and other stuff because there are no proper constrains.

    Once you fix pin locations assignments and see some leds blinking come back here and we will solve problems with .sdc.

  7. #7
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    Default Re: Constraining LEDs/Switches to VHDL onDE1-SoC

    I was able to get it to work with the pin planner tool. What is the purpose of the sdc and qsf. I feel as though for a more complicated project, I will probably need those but I am not sure how they fit into Quartus.

  8. #8
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    Default Re: Constraining LEDs/Switches to VHDL onDE1-SoC

    A .sdc file is for defining timing requirements for a design to guide the Fitter during place and route. See this training and its follow-ons:

    https://www.altera.com/support/train.../odsw1115.html

    .qsf is the Quartus settings file. Any assignments you create in Pin Planner or the Assignment Editor are stored there.

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